Invalidity dossier

US 5086429

Fault-tolerant digital computing system with reduced memory redundancy

Current assignee: Honeywell Inc

Added 9/23/2026, 9:04:34 PM

At a glanceNo PTAB challengesNo litigation on file

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Patent summary

Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.

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Patent Overview: US 5,086,429 A

Title: Fault-tolerant digital computing system with reduced memory redundancy

Patent number: US5086429A
Application number: US07/506,714
Inventors: Scott L. Gray; Steven R. Thompson
Assignee: Honeywell Inc. (original assignee); assigned to Honeywell Inc. by assignment of interest
Priority/filing date: 1990-04-10
Publication (grant) date: 1992-02-04
Legal status: Expired – Lifetime; anticipated expiration 2010-04-10
Source: https://patents.google.com/patent/US5086429/en

Purpose. The invention addresses fault-tolerant digital computer architecture for applications requiring very high safety, such as an aircraft flight control computer. Its scope is expressly limited to hardware fault tolerance, not software faults. It aims for a substantial improvement in safety using a lower degree of redundancy than previously disclosed, deliberately sacrificing error correction capability (which would improve availability) to gain safety.

Plain-language scope. The patent describes a pair-spare (dual-dual) redundancy architecture in which two pairs of substantially identical processors each run the same program simultaneously. One pair is "active" and holds the system bus; the other is a "hot stand-by" pair. Within each pair, the two processors share a common memory, reducing the memory redundancy otherwise required—prior pair-spare arrangements are described as imposing 4X memory replication. Each processor has its own address and data buses; bus monitors (9A/9B, 10A/10B) detect discrepancies in address, data, and control signals within a pair. Error detection logic (11A/11B, 12A/12B) uses linear block code generation and syndrome generators: on writes, check bits are created and stored with the data; on reads, the code word is checked and, if an error is found, a signal tells the bus monitor logic to switch the stand-by pair to active. The faulted pair records the fault and may stay faulted or, for a transient fault, become the stand-by pair. The result is described as a fail-operative, fail-passive system.

What the excerpt does not establish. It does not establish claims text, actual claim scope, validity, infringement, litigation, ownership transfers beyond the recorded assignment, or the content of prior art beyond the brief characterizations quoted above.

Generated 10/1/2026, 9:40:59 PM

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Proceedings on file (0)

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PTAB challenges

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Assignment history

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Prior art

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Obviousness

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Derivative works

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