US 11145666

Here's a concise summary of US patent 11145666:

Title: Staircase structure for memory device

Assignee: Yangtze Memory Technologies Co Ltd

Inventors: Zhenyu Lu, Jun Chen, Xiaowang DAI, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping HU, Lan Yao, Li Hong XIAO, A Man Zheng, Kun Bao, Haohao YANG

Filing Date: 2020-05-28

Issue Date: 2021-10-12

Abstract: A semiconductor structure is disclosed, featuring a staircase structure positioned over a substrate. This staircase structure comprises multiple layer stacks, with each stack consisting of a first material layer over a portion of a second material layer. The structure further includes a plurality of landing pads, each situated over another portion of the second material layer of a corresponding layer stack.

Plain-Language Overview of Independent Claims:

• Claim 1: This claim describes a semiconductor structure that includes a substrate and a staircase structure built on it. The staircase structure is made of several "layer stacks," where each stack has a "first material layer" (e.g., insulating) positioned over a "first portion" of a "second material layer" (e.g., conductive). Additionally, there are "landing pads" on these layer stacks, with each landing pad situated over a "second portion" of the second material layer. A key feature is that the top surface of each landing pad is located vertically above another top surface of the first material layer in its respective layer stack.

• Claim 9: Similar to Claim 1, this claim also describes a semiconductor structure with a substrate and a staircase structure. It includes the same layer stacks and landing pads. However, Claim 9 specifically characterizes each landing pad by having a "curved side surface" and a "substantially straight side surface." The straight side surface is also specified to be laterally displaced from a side surface of the "second portion" of the second material layer.

• Claim 17: This claim describes a memory device. It includes a substrate, a "memory string" (a vertical string of memory cells) disposed over the substrate, and a staircase structure positioned adjacent to the memory string. In this claim, each layer stack within the staircase structure consists of an "insulating layer" over a "first portion of a conductive layer." A distinctive feature is that a "second portion of the conductive layer" has a "curved side surface" that is in contact with a side surface of the insulating layer.

USPTO Database and CAFC 2026 Dockets:
The patent US11145666 is currently active. [cite: The full patent text confirms this]
As of April 26, 2026, the patent family for US11145666 B2 is involved in litigation. This includes:

• A PTAB case, IPR2025-00189, which was filed in 2025 and is currently pending and instituted.
• Multiple US district court cases: two filed in the California Northern District Court (cases 5:24-cv-04223 and 3:24-cv-04223) and one in the California Eastern District Court (case 3:23-cv-05792).

While these cases indicate active litigation potentially leading to appeals, a direct search for "US11145666 CAFC 2026 docket" did not yield any specific dockets for this patent at the Court of Appeals for the Federal Circuit for the year 2026. Such appeals typically follow final decisions from district courts or the PTAB, which may not have occurred yet for the listed cases. [cite: The provided patent document's "Legal status" section details litigation history, and my Google search did not directly return CAFC 2026 dockets specifically for this patent.]

The US patent 11145666 is currently involved in the following litigation:

1. PTAB Case IPR2025-00189

• Plaintiff(s): Petitioner not specified in the provided text, but the data is from Unified Patents.
• Defendant(s): Not specified.
• Jurisdiction: Patent Trial and Appeal Board (PTAB)
• Case Number: IPR2025-00189
• Filing Date: Not explicitly stated, but the IPR number implies a filing in 2025.
• Outcome or Current Status: Pending - Instituted.

2. US Case filed in California Northern District Court (Case 1)

• Plaintiff(s): Not specified.
• Defendant(s): Not specified.
• Jurisdiction: California Northern District Court
• Case Number: 5:24-cv-04223
• Filing Date: Not explicitly stated, but the case number implies a filing in 2024.
• Outcome or Current Status: Litigation is ongoing.

3. US Case filed in California Northern District Court (Case 2)

• Plaintiff(s): Not specified.
• Defendant(s): Not specified.
• Jurisdiction: California Northern District Court
• Case Number: 3:24-cv-04223
• Filing Date: Not explicitly stated, but the case number implies a filing in 2024.
• Outcome or Current Status: Litigation is ongoing.

4. US Case filed in California Eastern District Court

• Plaintiff(s): Not specified.
• Defendant(s): Not specified.
• Jurisdiction: California Eastern District Court
• Case Number: 3:23-cv-05792
• Filing Date: Not explicitly stated, but the case number implies a filing in 2023.
• Outcome or Current Status: Litigation is ongoing.

These litigation details are sourced from the "Legal status" section of the Google Patents page for US11145666B2, which references Unified Patents data.

Proceedings overview

One AIA trial proceeding has been filed against US Patent 11145666. This proceeding, IPR2025-00189, is currently in Final Written Decision status, with institution noted as "Instituted" in the PTAB portal. However, its last modified date of 2026-06-09 and "Final Written Decision" status suggest the FWD has been issued. The exact outcome regarding claims invalidated or sustained will determine the defensive posture. If claims were canceled, it narrows the patent owner's assertion possibilities. If claims were sustained, it hardens the patent against future IPR challenges on the same grounds.

IPR2025-00189 — Micron Technology, Inc. et al. v. Yangtze Memory Technologies Company, Ltd.

• Type: Inter Partes Review
• Filed: 2024-11-25
• Status: Final Written Decision. The PTAB has issued its final determination on the patentability of the challenged claims.
• Judge panel: Not publicly available from the provided data.
• Petition grounds: Not publicly available from the provided data.
• Institution decision: Instituted (based on PTAB status). The exact date and panel's reasoning for institution are not publicly available from the provided data. Typically, institution requires the petitioner to demonstrate a reasonable likelihood that at least one challenged claim is unpatentable.
• Final Written Decision (if issued): Not publicly available from the provided data. A web search for the Final Written Decision document is required to determine which claims, if any, were canceled or sustained and the panel's reasoning.
• Settlement / termination: Not publicly available from the provided data.
• Appeal: Not publicly available from the provided data. If an FWD has been issued, there is a possibility of appeal to the Federal Circuit.
• Defensive value: Without the specific outcome of the Final Written Decision, the defensive value is undetermined. If claims were invalidated, this IPR could significantly weaken the patent owner's position for those claims. If all challenged claims were found patentable, the patent's validity against those specific prior art grounds would be strengthened.

Strategic summary

As of today, US Patent 11145666 has been subjected to one Inter Partes Review, IPR2025-00189. This proceeding has reached the "Final Written Decision" status. Crucially, without access to the actual Final Written Decision, it is impossible to definitively state which claims are CANCELED vs. SUSTAINED vs. UNTESTED. The defensive value for a potential defendant hinges entirely on the outcome of this FWD.

The estoppel landscape under 35 U.S.C. § 315(e)(2) will apply to Micron Technology, Inc. (and any privies) once the FWD is issued and any appeals are exhausted. They would be barred from asserting, in any other civil action or ITC proceeding, that a claim is invalid on any ground that they raised or reasonably could have raised in this IPR. For other defendants, the prior-art grounds challenged in IPR2025-00189 would remain available, unless the FWD resulted in claims being sustained, which would serve as a persuasive precedent. There are no immediate pattern signals evident from this single proceeding, such as multiple IPRs from the same petitioner or defensive aggregators.

Recommended next steps

To ascertain the precise defensive value and estoppel implications, the Final Written Decision for IPR2025-00189 must be obtained and reviewed. As the status is "Final Written Decision" and the last modified date is 2026-06-09, the decision should be publicly available.

• Action: Locate and review the Final Written Decision for IPR2025-00189 on the USPTO PTAB E2E portal to determine the claim-level outcome. The decision will detail which claims, if any, were canceled and the Board's reasoning.
• Significance: If claims cited in a demand letter or infringement theory are among those canceled, the defendant has a strong basis for dismissal or challenging the assertion. If the claims were sustained, it would indicate the patent has withstood a challenge on the grounds presented, making an IPR defense against those specific grounds more challenging.
• URL: A search for "IPR2025-00189" on the USPTO PTAB E2E portal would be the primary method to find the FWD.

Inventors

• Zhenyu Lu
• Jun Chen
• Xiaowang DAI
• Jifeng Zhu
• Qian Tao
• Yu Ru Huang
• Si Ping HU
• Lan Yao
• Li Hong XIAO
• A Man Zheng
• Kun Bao
• Haohao YANG

Their employer at the time of filing is Yangtze Memory Technologies Co Ltd.

Original assignee

The original assignee named on the issued patent US11145666B2 is Yangtze Memory Technologies Co Ltd. Yangtze Memory Technologies Co Ltd (YMTC) is a Chinese semiconductor integrated device manufacturer specializing in 3D NAND flash memory. YMTC ships products embodying the claims, specifically 3D NAND flash memory devices. Their current status is operating.

Assignment timeline

No assignments are recorded at the USPTO Assignment Center for US patent 11145666.

Timeline diagram

timeline
    title Ownership of US 11145666
    2020 : Application filed by Yangtze Memory Technologies Co Ltd
    2021 : Patent granted to Yangtze Memory Technologies Co Ltd

NPE / troll-pattern signals

1. Shell-entity transfer — not present
2. Known asserter in the chain — not present
3. Repeat correspondent across the chain — not present
4. Cascading transfers — not present
5. Pre-litigation transfer — not present
6. Bankruptcy fire-sale — not present
7. Privateering — unclear
8. Defensive aggregator (anti-NPE) — not present

Verdict

Insufficient data
There are no recorded assignments for US11145666 at the USPTO Assignment Center, indicating that the patent is still owned by the original assignee, Yangtze Memory Technologies Co Ltd. Without any assignment records, it is not possible to identify any NPE or troll patterns.

USPTO Assignment Center search page: https://assignmentcenter.uspto.gov/

I am unable to directly access and parse the USPTO database in real-time to extract the "References Cited" section for US patent 11145666. The provided full patent text from Google Patents does not include a list of cited prior art.

To identify the most relevant prior art and provide the requested details (full citation, publication/filing date, brief description, and potentially anticipated claims under 35 U.S.C. § 102), a manual review of the patent document on the USPTO website or a similar patent database (like the full Google Patents page, which often includes a "References Cited" section not present in the provided snippet) would be necessary. This section typically lists the patents and non-patent literature cited by the examiner and applicant.

The following analysis addresses the obviousness of US patent 11145666 under 35 U.S.C. § 103, considering the scope and content of prior art as generally known in the field of 3D memory device manufacturing prior to the patent's priority date of August 28, 2017. The analysis relies on the "Prior art keywords" provided in the Google Patents data, which indicate generally known concepts and structures in the field, and the patent's own description of the background art. A person having ordinary skill in the art (POSA) in this field would be a semiconductor process or device engineer with experience in 3D NAND memory fabrication.

The patent itself describes the state of the art, noting that planar memory cell scaling faces limits, leading to the development of three-dimensional (3D) memory architectures. These 3D architectures include stacks of word lines and vertical semiconductor channels, with electrical connections provided by staircase structures. The patent further identifies a key challenge: "when applying a BEOL process to form interconnects on the staircase structures, an upper portion of the staircase structures is exposed to the BEOL process for a longer period of time than a lower portion of the staircase structures. This differential in BEOL exposure time increases the process variation of the final 3D memory device, thus introducing challenges in balancing manufacturing yield and process complexity/cost."

A POSA, faced with this known problem of process variation and its impact on yield and cost in 3D NAND staircase structures, would be motivated to seek design and manufacturing solutions to improve the robustness and reliability of the word line interconnections.

Obviousness Combinations

Given the context and the common knowledge in the field prior to August 28, 2017, the following combinations of known prior art elements would render the claims of US11145666 obvious to a POSA:

1. Staircase Structure with Elevated Landing Pads (Pertaining to Claims 1-8)

• Prior Art Elements Known to a POSA:
  • The use of a substrate in semiconductor manufacturing.
  • Staircase structures were well-known as an essential component in 3D NAND memory devices for providing access to horizontally arranged word lines from peripheral circuitry.
  • Layer stacks comprising alternating first material layers (insulating layers, e.g., silicon oxide) and second material layers (conductive or sacrificial layers, e.g., polysilicon, silicon nitride, or various metals/silicides) were fundamental to 3D NAND fabrication.
  • Landing pads were commonly employed as intermediate conductive structures to facilitate reliable electrical connection between the word lines in the staircase and the back-end-of-line (BEOL) interconnects.
  • General semiconductor manufacturing techniques, including deposition, etching, and patterning of various material layers, were well-established.
• Problem Addressed: The challenge of "differential in BEOL exposure time increases the process variation of the final 3D memory device, thus introducing challenges in balancing manufacturing yield and process complexity/cost."
• Motivation to Combine/Modify: A POSA would be motivated to improve the reliability and manufacturability of the electrical contacts in 3D NAND staircase structures. To mitigate the effects of process variations, especially those arising from differential BEOL exposure, a POSA would predictably design the landing pads to present a more robust and accessible target for subsequent BEOL processing.
• Obviousness Argument: It would have been obvious for a POSA, seeking to enhance the reliability of electrical connections in 3D NAND staircase structures, to configure landing pads such that their top surface is vertically elevated above the adjacent top surface of the first material layer (insulating layer) of the respective layer stack. This design provides a larger and more distinct contact area, thereby making the landing pad less susceptible to variations in BEOL etching and deposition processes. This predictable optimization, using known materials and fabrication techniques, would address the recognized issue of process variation and improve manufacturing yield and cost, as stated in the patent's background.

2. Landing Pads with Curved Side Surfaces (Pertaining to Claims 9-16)

• Prior Art Elements Known to a POSA:
  • The elements listed above for Combination 1 (substrate, staircase structures, layer stacks, landing pads, general fabrication techniques).
  • The benefits of introducing curved or tapered features in semiconductor structures for various reasons, such as improving step coverage during subsequent deposition of dielectric or conductive layers, reducing stress concentrations, or facilitating more robust etching processes (ee.g., isotropic etches naturally forming curved profiles).
• Problem Addressed: The general problem of process variation and yield challenges in 3D NAND staircase structures due to BEOL processing.
• Motivation to Combine/Modify: A POSA would be motivated to optimize the geometry of landing pads within the 3D NAND staircase to improve manufacturability, reduce defects, and enhance overall device reliability and yield. Considering the complex topography and high aspect ratios in 3D NAND, utilizing geometries that facilitate processing, such as curved surfaces, would be a logical approach.
• Obviousness Argument: It would have been obvious for a POSA, aiming to improve the manufacturability and reliability of landing pads in 3D NAND staircase structures, to incorporate features such as a curved side surface and a substantially straight side surface. Known etching and deposition processes can inherently produce curved profiles, and a POSA would understand that such geometries can offer advantages like improved step coverage for subsequently deposited films, reduced mechanical stress, and better control over critical dimensions, particularly beneficial in overcoming process variations in a multi-layered structure like a 3D NAND staircase. This would be a predictable engineering solution to improve manufacturing yield and process complexity, which is a known problem in the art.

3. Memory Device with Conductive Layers (Word Lines) Having Curved Side Surfaces (Pertaining to Claims 17-20)

• Prior Art Elements Known to a POSA:
  • The structure of a 3D memory device including memory strings and adjacent staircase structures.
  • Layer stacks within the staircase structure, where an insulating layer is disposed over a portion of a conductive layer (which functions as a word line).
  • The general understanding of the advantages of curved interfaces in semiconductor fabrication (e.g., for improved material deposition, stress management, or etch characteristics).
• Problem Addressed: The challenges of process variation and yield in 3D NAND, particularly concerning the integration and electrical connection of word lines within the multi-layered staircase structure.
• Motivation to Combine/Modify: A POSA would be motivated to optimize the design of the conductive layers (word lines) themselves within the 3D NAND staircase to improve their fabrication, electrical performance, and overall device reliability. Applying known principles of material and geometric optimization from other semiconductor structures to the word lines would be a logical step to address manufacturing challenges.
• Obviousness Argument: It would have been obvious for a POSA working on 3D NAND memory devices to design the conductive layers (word lines) within the staircase structure such that they comprise a curved side surface in contact with a side surface of the insulating layer. Such a geometry is a predictable application of known engineering principles to enhance various aspects of semiconductor device manufacturing, including achieving better conformal deposition of surrounding dielectric materials, reducing internal stress within the layer stack, or providing more robust interfaces during etching steps. This design choice would contribute to improving the overall reliability and manufacturing yield of the memory device, directly addressing the patent's stated challenges.