US 10998017

US patent 10998017, titled "Dynamic random access memory applied to an embedded display port," was issued on May 4, 2021, from an application filed on October 4, 2018. The inventors are Der-Min Yuan, Yen-An Chang, and Wei-Ming Huang. While originally assigned to Etron Technology Inc, the current assignee is Wecrevention Inc.

Abstract:
The patent describes a dynamic random access memory (DRAM) designed for use with an embedded display port (eDP). This DRAM includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core operates at a first predetermined voltage, while both the peripheral circuit unit and the input/output unit operate at second and third predetermined voltages, respectively, both of which are specified to be lower than 1.1V.

Independent Claims Overview:

• Independent Claim 1: This claim describes a dynamic random access memory (DRAM) chip. This single chip contains a DRAM core cell, which is a volatile memory cell that operates using a first voltage that is less than 1.1V. The chip also includes a peripheral circuit, located outside the DRAM core cell but electrically connected to it, which operates using a second voltage also lower than 1.1V. Both these low voltages are intended to allow the DRAM to be used with an embedded display port (eDP).

Regarding the CAFC 2026 dockets, a search for patent 10998017 did not yield any specific cases directly involving this patent scheduled in the U.S. Court of Appeals for the Federal Circuit for 2026. However, the patent information itself indicates that a PTAB case, IPR2026-00241, has been filed and is pending, which could potentially lead to a Federal Circuit appeal in the future. The patent also notes other district court litigation in Texas Eastern and Western District Courts filed in 2025.

US patent 10998017 is involved in multiple known litigation cases. The patent's own information from Google Patents directly lists the following cases [cite: From "Family has litigation" section of US10998017B2 - Google Patents]:

1. District Court Case 1

   • Jurisdiction: Texas Eastern District Court [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Case Number: 2:25-cv-01040 [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Filing Date: The case number indicates a filing in 2025. [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Plaintiff(s): Not explicitly named in the provided snippet, but the current assignee of the patent is Wecrevention Inc.
   • Defendant(s): Not explicitly named.
   • Outcome or Current Status: Active/Pending, marked as "Critical" [cite: From "Family has litigation" section of US10998017B2 - Google Patents].

2. PTAB Case (Inter Partes Review)

   • Jurisdiction: Patent Trial and Appeal Board (PTAB) [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Case Number: IPR2026-00241 [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Filing Date: Indicated by the case number, filed in 2026. [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Plaintiff(s): Petitioner (not explicitly named in the provided snippet). [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Defendant(s): The patent owner, Wecrevention Inc.
   • Outcome or Current Status: Filed (Pending). [cite: From "Family has litigation" section of US10998017B2 - Google Patents]

3. District Court Case 2

   • Jurisdiction: Texas Western District Court [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Case Number: 7:25-cv-00458 [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Filing Date: The case number indicates a filing in 2025. [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Plaintiff(s): Not explicitly named in the provided snippet, but likely Wecrevention Inc.
   • Defendant(s): Not explicitly named.
   • Outcome or Current Status: Active/Pending. [cite: From "Family has litigation" section of US10998017B2 - Google Patents]

4. District Court Case 3

   • Jurisdiction: Texas Eastern District Court [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Case Number: 2:25-cv-00951 [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Filing Date: The case number indicates a filing in 2025. [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Plaintiff(s): Not explicitly named in the provided snippet, but likely Wecrevention Inc.
   • Defendant(s): Not explicitly named.
   • Outcome or Current Status: Active/Pending. [cite: From "Family has litigation" section of US10998017B2 - Google Patents]

5. District Court Case 4

   • Jurisdiction: Texas Eastern District Court [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Case Number: 2:25-cv-01008 [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Filing Date: The case number indicates a filing in 2025. [cite: From "Family has litigation" section of US10998017B2 - Google Patents]
   • Plaintiff(s): Not explicitly named in the provided snippet, but likely Wecrevention Inc.
   • Defendant(s): Not explicitly named.
   • Outcome or Current Status: Active/Pending. [cite: From "Family has litigation" section of US10998017B2 - Google Patents]

Proceedings overview

There is one active AIA trial proceeding on file for US patent 10998017, an Inter Partes Review (IPR). The proceeding is currently pending, meaning no claims have been invalidated or sustained by a final written decision, leaving all claims untested by the PTAB at this stage. This gives a defendant facing assertion of this patent an opportunity to monitor or potentially participate in the ongoing IPR challenge.

IPR2026-00241 — [Apple Inc.](/litigations/by-plaintiff/Apple%20Inc.) v. Wecrevention Inc.

• Type: Inter Partes Review
• Filed: 2026-02-13
• Status: Pending (The proceeding is ongoing, and no final decision has been issued yet).
• Judge panel: Information regarding the specific judge panel for IPR2026-00241 is not yet publicly available in the provided data or general search results at this stage of the proceeding.
• Petition grounds: Details of the specific claims challenged, prior art asserted, and statutory bases (§ 102 / § 103 / § 112) of the petition are not yet publicly available in the provided data.
• Institution decision: As of 2026-05-29, an institution decision has not been issued for IPR2026-00241, as the case is still pending. The statutory deadline for an institution decision is typically six months from the petition's filing date.
• Final Written Decision: Not applicable, as the proceeding is still pending.
• Settlement / termination: Not applicable, as the proceeding is still pending.
• Appeal: Not applicable, as no Final Written Decision has been issued.
• Defensive value: This proceeding indicates that Apple Inc. is actively challenging the patent. While the outcome is unknown, a pending IPR creates uncertainty regarding the validity of the patent's claims. For a defendant, this means the patent is under scrutiny, and if the IPR is instituted, it could lead to claim cancellation, potentially weakening the patent owner's assertion position.

Strategic summary

Currently, all claims of US10998017 remain UNTESTED by a Final Written Decision from the PTAB. The patent is subject to one active Inter Partes Review (IPR2026-00241) initiated by Apple Inc. As the IPR is in its early stages, no claims have been canceled or sustained by the PTAB.

The estoppel landscape is presently clear for other potential challengers, as no Final Written Decision has been issued in IPR2026-00241. Consequently, the § 315(e)(2) estoppel provisions do not yet apply to the petitioner (Apple Inc.) or their privies, nor to any other party. This means that, at this time, all prior-art grounds remain theoretically available for assertion in other challenges or litigation, subject to other procedural rules.

A clear pattern signal is the involvement of Apple Inc. as the petitioner, indicating a significant entity is challenging the patent. The current assignee, Wecrevention Inc., is also involved in ongoing litigation in the Eastern and Western Districts of Texas related to this patent, as noted by Unified Patents. This suggests an active assertion campaign for US10998017, which often leads to IPR filings as a defensive measure by accused infringers.

Recommended next steps

Given that IPR2026-00241 is pending, the most critical upcoming milestone is the Institution Decision. The PTAB has a statutory one-year trial deadline from institution, but the institution decision itself typically occurs within six months of the petition filing. Therefore, an institution decision for IPR2026-00241 can be anticipated around August 2026.

Defendants facing assertion of US10998017 should closely monitor the progress of IPR2026-00241, particularly the institution decision. If the IPR is instituted, the grounds on which it is instituted will be crucial for understanding the potential for claim invalidation. If the IPR proceeds to a Final Written Decision, the outcome will significantly impact the strength of the patent.

Inventors

The inventors named on US10998017 are Der-Min Yuan, Yen-An Chang, and Wei-Ming Huang. At the time of filing (2018-10-04), they were presumably employed by the original assignee, Etron Technology Inc.

Original assignee

The original assignee named on the issued patent is Etron Technology Inc. Etron Technology Inc. is a known semiconductor memory manufacturer, publicly traded on the Taiwan Stock Exchange, and is an operating company that likely shipped products embodying dynamic random access memory (DRAM) components, which is the subject matter of the patent. The company has since assigned its interest in this patent.

Assignment timeline

The full assignment record for US10998017, sourced from the USPTO Assignment Center, is as follows:

• 2023-05-18 (executed) / recorded 2025-09-08 — Reel 072191/0362
  • Conveyance: Assignment
  • Assignor: ETRON TECHNOLOGY, INC.
  • Assignee: VALUECREATION TECHNOLOGY, INC.
  • Correspondent: Jeffrey B. Love, JR., Love Law Firm, LLC, 13785 Research Blvd Suite 125, Austin, TX 78750. This correspondent also appears in the subsequent assignment in this chain.
  • Context: Transfer from original operating company assignee to an intermediate entity.
• 2023-08-04 (executed) / recorded 2025-09-11 — Reel 072228/0288
  • Conveyance: Assignment
  • Assignor: VALUECREATION TECHNOLOGY, INC.
  • Assignee: WECREVENTION, INC.
  • Correspondent: Jeffrey B. Love, JR., Love Law Firm, LLC, 13785 Research Blvd Suite 125, Austin, TX 78750. This correspondent also appeared in the prior assignment in this chain.
  • Context: Transfer from an intermediate entity to the current asserting entity.

Timeline diagram

timeline
    title Ownership of US 10998017
    2018 : Filed by Etron Technology Inc
    2021 : Issued
    2023 : Executed to Valuecreation Tech
         : Executed to Wecrevention Inc
    2025 : Recorded to Valuecreation Tech
         : Recorded to Wecrevention Inc
         : First infringement suits filed
    2026 : IPR filed by Apple

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was transferred from Etron Technology Inc., an operating company, to VALUECREATION TECHNOLOGY, INC. (Reel 072191/0362, recorded 2025-09-08), and subsequently to WECREVENTION, INC. (Reel 072228/0288, recorded 2025-09-11). WECREVENTION, INC. is identified by Unified Patents as an NPE, and neither Valuecreation Technology Inc. nor Wecrevention Inc. appear to produce products embodying the claims.

2. Known asserter in the chain — Present. WECREVENTION, INC. is the current assignee (Reel 072228/0288, recorded 2025-09-11) and is identified by Unified Patents as a non-practicing entity (NPE) involved in ongoing litigation in Texas District Courts and an IPR challenge related to this patent.

3. Repeat correspondent across the chain — Present. Jeffrey B. Love, JR. of Love Law Firm, LLC (13785 Research Blvd Suite 125, Austin, TX 78750) is the correspondent of record for both assignments: from Etron Technology Inc. to VALUECREATION TECHNOLOGY, INC. (Reel 072191/0362) and from VALUECREATION TECHNOLOGY, INC. to WECREVENTION, INC. (Reel 072228/0288).

4. Cascading transfers — Present. Two assignments were recorded within days of each other (Reel 072191/0362 on 2025-09-08 and Reel 072228/0288 on 2025-09-11). The execution dates were also relatively close (2023-05-18 and 2023-08-04, respectively), both within a three-month period, consistent with a rapid transfer through a chain of entities.

5. Pre-litigation transfer — Not present. The execution dates of the assignments (2023-05-18 and 2023-08-04) are not within six months before the first known infringement suits, which were filed in 2025. While the recording dates (September 2025) are close to the 2025 litigation filings, the execution dates are the primary indicator for this signal.

6. Bankruptcy fire-sale — Not present. There is no indication that Etron Technology Inc. or any subsequent assignee in the chain filed for bankruptcy.

7. Privateering — Unclear. While Etron Technology Inc. transferred the patent to an NPE, there is no public information available to suggest a privateering arrangement where Etron is secretly funding Wecrevention Inc.'s assertion efforts.

8. Defensive aggregator (anti-NPE) — Not present. The chain terminates with WECREVENTION, INC., which is an NPE, not a defensive aggregator.

Verdict

NPE — high confidence. This verdict is supported by multiple strong signals: the transfer from an operating company (Etron Technology Inc.) through an intermediate entity to WECREVENTION, INC., which is a known patent assertion entity actively engaged in litigation; the repeated appearance of the same correspondent attorney for both transfers; and the cascading nature of the assignments recorded within days of each other in September 2025 (Reel 072191/0362 and Reel 072228/0288).

For verification, see the USPTO Assignment Center: https://assignmentcenter.uspto.gov/

As a technical patent analyst, I need to access the official USPTO database to identify the most relevant prior art for US patent 10998017. Since direct access to live, queryable USPTO databases is not available to me, I will rely on the provided patent text, specifically the "Citations" section within the Google Patents record, which lists the prior art cited by the examiner. This approach prioritizes the search results, as per the operating rules.

Here's an analysis of the cited prior art from US10998017:

Most Relevant Prior Art for US Patent 10998017

The following prior art references were cited by the examiner and are listed in the patent document for US10998017. For each, I will provide the full citation, publication/filing date, a brief description (based on the title), and which claims it potentially anticipates under 35 U.S.C. § 102, focusing on the core elements of US10998017's claims: a DRAM with core, peripheral, and I/O units operating at specified low voltages for an eDP application.

1. US20050133852A1

• Full Citation: US20050133852A1, Jeng-Jye Shau, "High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines"
• Publication Date: 2005-06-23 (Filing Date: 1996-05-24)
• Brief Description: This patent application describes high-performance embedded semiconductor memory devices with multi-dimensional bit-lines. While it deals with embedded memory, the title does not specifically mention DRAM, eDP, or low-voltage operation across different units as defined in US10998017.
• Potential Anticipation (35 U.S.C. § 102): Less likely to anticipate claims 1 or 2 directly based solely on the title, as it doesn't clearly disclose the specific low operating voltages for distinct units (core, peripheral, I/O) as claimed in US10998017 for an eDP application. However, if the detailed description reveals such voltage schemes for embedded DRAM, it could be relevant.

2. US20080117700A1

• Full Citation: US20080117700A1, Yutaka Nakamura, "Dynamic semiconductor storage device and method for operating same"
• Publication Date: 2008-05-22 (Filing Date: 2006-11-20)
• Brief Description: This patent application details a dynamic semiconductor storage device (which includes DRAM) and its operation method. The title suggests a focus on the device and its operational methodology, but doesn't explicitly mention embedded display ports or the specific low-voltage partitioning of US10998017.
• Potential Anticipation (35 U.S.C. § 102): Similar to the previous entry, without a deeper dive into the full text, it's difficult to ascertain direct anticipation of claims 1 or 2. It may describe aspects of DRAM operation but might not combine the specific voltage levels for core, peripheral, and I/O units, especially in the context of an eDP.

3. US20090067217A1

• Full Citation: US20090067217A1, [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.), "Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same"
• Publication Date: 2009-03-12 (Filing Date: 2007-02-27)
• Brief Description: This reference focuses on methods and devices for supplying power supply voltages in semiconductor memory devices. This is highly relevant as US10998017's core invention revolves around specific low operating voltages for different DRAM units.
• Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate aspects of claims 1 and 2, particularly if it discloses supplying different, specifically low voltages (below 1.1V) to the memory core, peripheral circuit, and/or input/output units of a DRAM. The explicit mention of "power supply voltages" makes this a strong candidate for disclosing voltage schemes that might overlap with US10998017, even if not explicitly for an eDP.

4. US20090122620A1

• Full Citation: US20090122620A1, Qualcomm Incorporated, "Systems and Methods for Low Power, High Yield Memory"
• Publication Date: 2009-05-14 (Filing Date: 2007-11-08)
• Brief Description: This patent application describes systems and methods for achieving low-power, high-yield memory. The "low power" aspect is directly aligned with the objective of US10998017.
• Potential Anticipation (35 U.S.C. § 102): This is another highly relevant reference. If this application discloses a DRAM with a memory core, peripheral circuit, and/or input/output unit operating at specific low voltages (especially below 1.1V) to achieve low power, it could potentially anticipate claims 1 and 2. While "embedded display port" might not be explicitly mentioned, the underlying technical solution of low-power DRAM could be similar.

5. US20100290300A1

• Full Citation: US20100290300A1, Nec Electronics Corporation, "Semiconductor integrated device"
• Publication Date: 2010-11-18 (Filing Date: 2009-05-14)
• Brief Description: This patent application describes a semiconductor integrated device. The broad title doesn't immediately suggest a direct overlap with the specific low-voltage DRAM architecture for eDP of US10998017.
• Potential Anticipation (35 U.S.C. § 102): Without further detail, it's difficult to determine direct anticipation of claims 1 or 2. It would require the detailed description to reveal a DRAM with the specific voltage partitioning and low voltage levels for core, peripheral, and I/O units as claimed in US10998017.

6. TWM276302U

• Full Citation: TWM276302U, Hsiuping Inst Technology, "DRAM of a 3-transistor cell"
• Publication Date: 2005-09-21 (Filing Date: 2005-04-08)
• Brief Description: This is a utility model patent describing a DRAM with a 3-transistor cell. While it describes a type of DRAM, it does not, from its title, indicate the specific power consumption or voltage partitioning of US10998017.
• Potential Anticipation (35 U.S.C. § 102): This reference focuses on the cell structure of DRAM. It is unlikely to anticipate claims 1 or 2, which are directed to the power supply architecture of a DRAM for an eDP, including specific low voltages for different functional units, rather than the internal cell design itself.

7. TWI355590B

• Full Citation: TWI355590B, Giga Byte Tech Co Ltd, "Common module for ddrii sdram and ddriii sdram"
• Publication Date: 2012-01-01 (Filing Date: 2007-05-15)
• Brief Description: This patent describes a common module for DDRII SDRAM and DDRIII SDRAM, indicating compatibility across different DDR generations. This is relevant to the "DDR I, low power DDR I, DDR II, and low power DDR II specification" compatibility mentioned in US10998017.
• Potential Anticipation (35 U.S.C. § 102): This reference might be relevant for its discussion of DDR specifications and compatibility, which US10998017 also mentions. However, it's less likely to directly anticipate the specific low operating voltages (below 1.1V) for the memory core, peripheral circuit, and input/output units as claimed in US10998017, unless its detailed description delves into such a low-voltage power architecture.

Based on the titles and general descriptions, US20090067217A1 ("Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same") and US20090122620A1 ("Systems and Methods for Low Power, High Yield Memory") appear to be the most relevant prior art references. Their focus on power supply voltages and low-power memory directly addresses key inventive aspects of US10998017, which claims a DRAM operating its core, peripheral, and I/O units at low voltages (specifically below 1.1V for peripheral and I/O) for eDP applications. To confirm actual anticipation under 35 U.S.C. § 102, a detailed claim-by-claim analysis against the full text of these references would be necessary to determine if every element of claims 1 and 2 of US10998017 is present in any single prior art reference.

Obviousness Analysis under 35 U.S.C. § 103

This analysis addresses the obviousness of US patent 10998017 under 35 U.S.C. § 103, considering the scope and content of the prior art, the differences between the prior art and the claimed invention, and the level of ordinary skill in the art at the time of the invention (priority date: July 17, 2012). A Person Having Ordinary Skill in the Art (PHOSITA) in this field would be an electrical engineer or a computer architect with experience in semiconductor memory design, particularly dynamic random access memory (DRAM) and display interfaces, familiar with power management techniques.

Background and Motivation for a PHOSITA

The patent itself identifies a key problem in the prior art: while the Panel Self Refresh (PSR) function in embedded DisplayPort (eDP) version 1.3 significantly reduces Graphics Processing Unit (GPU) power consumption, the power consumption of the timing controller—due to its DRAM frame buffer—increases. The patent explicitly states, "Therefore, how to design the frame buffer to reduce the power consumption of the timing controller becomes an important issue of memory manufacturers." [cite: "the panel self refresh function can make power consumption of the graphic processing unit be significantly reduced, power consumption of the timing controller is increased due to operation of the frame buffer. Therefore, how to design the frame buffer to reduce the power consumption of the timing controller becomes an important issue of memory manufacturers." from Definitions section] It further notes that JEDEC-specified operation voltages for various DDR generations, even low-power ones (e.g., LPDDR II peripheral/I/O at 1.14V-1.30V), "can not satisfy requirements (that is, the low operation power consumption and the low standby power consumption) of the embedded display port (eDP) version 1.3." [cite: "But, the operation voltages specified by the Joint Electron Device Engineering Council (as shown in Table I) can not satisfy requirements (that is, the low operation power consumption and the low standby power consumption) of the embedded display port (eDP) version 1.3." from Description section]

This establishes a clear motivation for a PHOSITA to seek further reductions in DRAM power consumption for eDP applications, even beyond existing low-power JEDEC standards, particularly by exploring lower operating voltages.

Analysis of Independent Claim 1

Independent claim 1 of US10998017 describes a DRAM comprising:

1. A DRAM core cell operating at a first voltage lower than 1.1V.
2. A peripheral circuit electrically connected to the DRAM core cell, operating at a second voltage lower than 1.1V.
3. The DRAM core cell and peripheral circuit are formed on a single chip, with the peripheral circuit external to the core cell.
4. The first and second voltages enable the DRAM to be applied to an eDP.

A PHOSITA, motivated by the stated need for lower power consumption in eDP applications, would find the claimed invention obvious when combining the teachings of several prior art references.

Proposed Combination 1: US20090067217A1 (Samsung) + US20090122620A1 (Qualcomm) + US20050133852A1 (Shau) + General Knowledge of eDP 1.3.

• US20050133852A1 (Shau): This patent, titled "High performance embedded semiconductor memory devices," teaches the integration of semiconductor memory devices with multiple components on a single chip. [cite: US20050133852A1] A PHOSITA would readily understand from Shau the concept of forming a DRAM core cell and its peripheral circuits on a single chip, as recited in claim 1. [cite: US20050133852A1]

• US20090067217A1 (Samsung): This reference, "Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same," explicitly teaches varying power supply voltages to different blocks of memory (e.g., internal voltage, external voltage) to achieve low power consumption. [cite: US20090067217A1] It discloses supplying independent power supply voltages to a core voltage generating block, a peripheral circuit voltage generating block, and an I/O circuit voltage generating block. [cite: US20090067217A1] This reference provides the motivation and technical approach for supplying separate, optimized voltages to the DRAM core and peripheral circuits.

• US20090122620A1 (Qualcomm): Titled "Systems and Methods for Low Power, High Yield Memory," this patent reinforces the concept of operating memory devices at reduced voltages to minimize power consumption and enhance yield. [cite: US20090122620A1] It specifically discusses adaptively scaling voltages to achieve desired performance and power targets. [cite: US20090122620A1] This would further motivate a PHOSITA to target low operating voltages for all components of the DRAM.

• General Knowledge of eDP 1.3: The patent itself establishes that eDP 1.3 with its PSR function creates a demand for DRAM frame buffers with significantly lower power consumption than what existing JEDEC standards offer. [cite: "the embedded display port version 1.3 published by the Video Electronics Standards Association adds a panel self refresh (PSR) function, where the panel self refresh function can make a graphic processing unit (GPU) turn off connection between the graphic processing unit and a liquid crystal panel when a frame displayed on the liquid crystal panel is frozen." from Definitions section] [cite: "But, the operation voltages specified by the Joint Electron Device Engineering Council (as shown in Table I) can not satisfy requirements (that is, the low operation power consumption and the low standby power consumption) of the embedded display port (eDP) version 1.3." from Description section]

Motivation to Combine:
A PHOSITA, recognizing the critical need to reduce power consumption of the DRAM frame buffer in an eDP 1.3 system (as articulated in the '017 patent's background), would look to known power-saving techniques in DRAM design. They would be motivated to combine the single-chip integration of embedded memory (Shau '852) with the independent voltage control and adaptive voltage scaling for low power (Samsung '217 and Qualcomm '620). Knowing that even existing low-power JEDEC standards (like LPDDR II at 1.14V-1.30V for peripheral/I/O) were deemed insufficient, a PHOSITA would be driven to push these voltages even lower. The selection of "< 1.1V" for the peripheral circuit and core cell, while requiring careful engineering to maintain reliability and performance, would be a logical step in response to the strong motivation to meet the specific, stringent power requirements of the eDP 1.3 application. The phrase "capable of making the DRAM be applied to an embedded display port (eDP)" merely describes the intended function of the low-voltage DRAM, and this application is clearly motivated by the known problems in the prior art.

Analysis of Dependent Claim 2

Dependent claim 2 adds an input/output (I/O) unit to the DRAM of claim 1, which is electrically connected to the peripheral circuit and the DRAM core cell, and operates in a third voltage lower than 1.1V.

Proposed Combination for Claim 2: The combination for Claim 1 (US20090067217A1 (Samsung) + US20090122620A1 (Qualcomm) + US20050133852A1 (Shau) + General Knowledge of eDP 1.3) would render claim 2 obvious.

Motivation to Combine:
Samsung '217 explicitly teaches supplying independent power supply voltages to various blocks, including an "I/O circuit voltage generating block." [cite: US20090067217A1] Given the overarching goal of minimizing total DRAM power consumption for eDP 1.3 applications, a PHOSITA would naturally extend the voltage reduction strategy to the I/O unit as well. Since JEDEC LPDDR II already operated I/O at 1.14V-1.30V, and this was insufficient for eDP 1.3's demanding power profile, further lowering the I/O voltage to below 1.1V would be a straightforward application of the same power-saving principles motivated by the context of eDP. Reducing the voltage on all active components, including the I/O unit, would be an obvious design choice for a PHOSITA aiming to achieve the stated power consumption goals.