US 10634563

I'll search for authoritative information on this patent number, including any litigation or CAFC 2026 docket activity.

Let me run more targeted searches for this specific patent and any related litigation.

Let me try to retrieve the remaining claims and check for any litigation involving the assignee.

US Patent 10,634,563 B2 — Analyst Summary

Sourcing note: The analysis below is grounded in the authoritative full text of the patent you supplied (fetched from https://patents.google.com/patent/[US10634563](/patent/US10634563)/en) plus corroborating search results. My web searches for the specific identifier 10634563 returned no litigation records — see the "Litigation / Docket Search" section, which is important and reported honestly.

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1. Bibliographic Data

Classification: G01J 9/02 (optical phase difference by interferometry), G01B 11/14, G01R 25/00 & 25/08 (phase-angle measurement; by counting standard pulses), G01R 29/26, H03D 13/00, H03L 7/00–7/091 (PLL details).

Assignee note: This is the Japanese national research institute AIST. The named inventor, Wataru Kokuyama, is the sole inventor, and the PCT/JP2015/081984 application previously proposed by the same inventor is referenced in the specification as the inventors' own earlier proposal.

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2. Abstract (verbatim)

"A count processor counts a zero crossing detection count C. A fraction processor for calculating a fraction Fⱼ (j=1 to L) of the zero crossing detection count on the basis of the digital signal at sampling timings immediately before a zero crossing specifying and when the zero crossing specifying, and computing a fraction processing parameter Gⱼ = Nⱼ − Fⱼ using a zero crossing detection number Nⱼ (0 ≤ Nⱼ ≤ N−1) in a period corresponding to a sampling count N necessary for averaging determined in advance. The averaging is performed according to the following formula, where C is the output of the count processor at the end of an averaging period and Gⱼ (j=1 to L) is L fraction processing parameters (L indicates the number of Gⱼ included between the averaging counts N) computed by the fraction processor, and the phase of the digital signal is computed, whereby the phase is calculated on the basis of an input signal digital value obtained by an AD converter."

The governing equation (Formula 1):
U = C − (1/N) Σ_{j=1..L} Gⱼ

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3. Plain-Language Overview of the Claims

Important scope caveat: The authoritative text provided contains the full text of claim 1 and claim 2, and claim 3 is truncated mid-sentence in the supplied document. I could independently confirm claims 1–2 and the opening of claim 3 via a Justia mirror (patents.justia.com/patent/10634563). I do not have reliable full text for claims 4–9 and will not fabricate them. See "Uncertainty" below.

Claim 1 — Independent (the phase measurement device)

A digital phase-measurement device for a periodic input signal, comprising four elements:

1. An AD converter that digitizes the periodic input signal at each predetermined sampling timing and outputs a digital signal;
2. A count processor that controls zero-crossing detection (detecting a change in sign of the digital signal) and counts/derives a zero-crossing detection count C at each sampling timing;
3. A fraction processor that computes a fraction Fⱼ (j = 1 to L) of the zero-crossing detection count from the digital signal values immediately before and at the zero-crossing, and further computes a fraction processing parameter Gⱼ = Nⱼ − Fⱼ, where Nⱼ (0 ≤ Nⱼ ≤ N−1) is the zero-crossing detection number within a period of predetermined sampling count N (number of data to be averaged); and
4. An averaging processor that averages the count processor value C (at period end) and the L fractions within the sampling-count-N period, using the formula U = C − (1/N)ΣGⱼ (L = number of Gⱼ in the averaging interval), thereby computing the phase of the digital signal.

In plain terms: digitize a periodic signal, count integer zero-crossings, add a sub-sample fractional correction at each crossing, and combine them over an averaging window to output a high-resolution phase — with no PLL, no second high-speed clock, and no memory-buffered post-processing.

Claim 2 — Dependent on Claim 1 (lost-zero-crossing correction)

When the outputs of the count processor and fraction processor are fed to a correcting unit, and the difference ΔGⱼ = Gⱼ₊₁ − Gⱼ between adjacent fraction parameters exceeds a predetermined threshold, the correcting unit:

• estimates the lost zero-crossing count from ΔGⱼ,
• adds that lost count to the count processor's zero-crossing count, and
• estimates the missing fraction parameter from the Gⱼ values immediately before and after the lost crossing.

Plain terms: a noise-robustness feature that detects missed (dropped) zero crossings and patches them in real time — useful where a weak optical return signal loses crossings.

Claim 3 — Dependent on Claim 1 (excess/false zero-crossing correction) — text truncated

By its opening wording (confirmed via the Justia mirror), claim 3 uses the same correcting-unit architecture and the same ΔGⱼ threshold test, but for the opposite error: it subtracts an erroneously/extra-detected zero-crossing count from C, and subtracts a value of the fraction parameter Gⱼ. The remainder of claim 3 is cut off in the source text; I cannot state its full scope with confidence.

Claims 4–9 — Not available in the supplied text

The patent recites 9 claims total. Beyond the dependents above, the specification also describes (i) a high-frequency-variation reduction processor (Formula 14 correction), and (ii) a phase-difference measurement device built from two of the claimed phase-measurement devices plus a subtractor. It is plausible, but not confirmed, that one of claims 4–9 is an independent claim to such a phase-difference measurement device (the "Means for Solving the Problems" section states the invention includes both a phase measurement device and a phase difference measurement device). I flag this as an inference, not a verified fact.

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4. Litigation / CAFC 2026 Docket Search

Per your instruction, I searched for docket activity tied specifically to the number 10634563 and to the assignee.

Result: I found no evidence of any district-court case, PTAB proceeding (IPR/PGR), or CAFC 2026 appeal involving US 10,634,563. Searches for the identifier returned only unrelated patents (e.g., 10,342,543; 10,270,633; 10,912,321; 11,129,163) — none of which should be confused with this patent per your strict-no-correction rule.

This is consistent with the patent's profile: it is a measurement-instrument patent owned by a government research institute (AIST), marked "Expired – Fee Related," with a lapsed EP counterpart (EP 3 447 505). Such patents rarely appear in US enforcement litigation.

Honest uncertainty statement: Absence of results across my searches is not proof that no proceeding exists. I did not obtain a direct hit on a live USPTO PatentCenter/Patent Trial and Appeal Board docket or a CAFC docket for this exact number. To reach high confidence you would need to query the USPTO Patent Public Search / PatentCenter APIs and the CAFC docket system directly by patent number and by assignee name — which those databases support but which my search tooling did not fully expose here.

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5. Related Family / Cross-Reference (clearly labeled)

• The specification references the inventors' own prior proposal, PCT/JP2015/081984, which corresponds to a separate, distinct patent — US 10,270,633 ("Phase measuring device and apparatuses using the phase measuring device"), also AIST/Kokuyama and sharing the count/fraction/averaging architecture, but with a broader integration-based averaging formula. This is a different patent number and must not be conflated with 10,634,563.
• EP counterpart EP 3 447 505 (application EP17792737.3) — granted, now lapsed/ceased.

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6. Summary of Confidence

I'll search for litigation involving US patent 10634563 across litigation databases and court records.

Let me try additional targeted searches across litigation databases.

Litigation Search — U.S. Patent No. 10,634,563

Bottom line

No litigation involving U.S. Patent No. 10,634,563 was found. My searches of litigation-focused sources (Unified Patents litigation portal, PTAB/docket materials, and general web coverage of district court and Federal Circuit activity) returned zero results tying this specific patent number to any filed case. I cannot report a plaintiff, defendant, jurisdiction, case number, filing date, or outcome because no such case appears to exist in the sources I could reach.

I want to be explicit about the limits of this answer rather than present speculation as fact:

• I did not obtain a live hit from the Unified Patents caselist, PACER, or a CAFC docket for this number.
• The searches I ran returned unrelated patents (e.g., 10,659,885 / 10,820,117 in the Taction v. Apple haptics dispute; various Unified Patents IPRs on other numbers). Those are different patents and must not be attributed to 10,634,563.
• Because I could not directly query PACER/Docket Navigator/Lex Machina dockets in this session, I cannot rule out a non-public, sealed, or very recent filing. Treat this as "none found," not "none exists."

Context on the patent (from the authoritative patent text provided)

• Patent: US 10,634,563 B2 — "Phase measurement device and instrument in which phase measurement device is applied"
• Inventor: Wataru KOKUYAMA
• Current/Original Assignee: National Institute of Advanced Industrial Science and Technology (AIST) — a Japanese national research institute
• Application No.: US 16/098,958; Filed: 2017-04-27; Priority: 2016-05-06; Granted: 2020-04-28
• Legal status: Expired — Fee Related; anticipated expiration 2037-04-27
• Family: appears to include EP 3,447,505 (EP 17792737.3), which is also reported as lapsed/not in force in the EU sources returned.

Why no litigation is plausible

This is a measurement/instrumentation patent (phase and phase-difference measurement for laser heterodyne interferometers, phase-noise measurement, etc.) owned by a government research institute, not a licensing/NPE entity. There is no indication in the record of enforcement activity, licensing campaigns, or assignment to a litigation-oriented holder. Combined with the Expired – Fee Related status, the absence of any litigation is consistent with a research-institute-held patent that was never asserted.

Recommended verification steps

To definitively confirm "no litigation," I would check these directly (which I could not fully execute here):

1. Unified Patents litigation portal — https://portal.unifiedpatents.com/litigation/caselist (search by patent number 10634563).
2. PACER / CourtListener RECAP — search dockets by patent number.
3. USPTO Patent Center / Global Dossier — review the patent's file history for any litigation-related submissions.
4. Docket Navigator or Lex Machina — the definitive commercial litigation databases.

If you'd like, I can attempt additional targeted searches on any of the above, or narrow by the assignee (AIST) rather than the patent number.

PTAB Proceedings Report — U.S. Patent No. 10,634,563

Patent: US 10,634,563 B2 — "Phase measurement device and instrument in which phase measurement device is applied"
Patent Owner / Assignee: National Institute of Advanced Industrial Science and Technology (AIST) — a Japanese national metrology/research institute
Inventors: Wataru Kokuyama
Priority date: 2016-05-06 | Filing date: 2017-04-27 | Grant date: 2020-04-28
Legal status (per Google Patents): Expired – Fee Related | Anticipated expiration: 2037-04-27

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Proceedings overview

Zero (0) AIA trial proceedings are on file against this patent. The USPTO Open Data Portal returns no IPR, PGR, CBM, or derivation proceeding for US 10,634,563 as of the most recent ingest, and independent web research surfaced no petition, institution decision, final written decision, or appeal referencing this patent number or its pre-grant publication (US 2019/0086270 A1). Because there is nothing to characterize, there is no "claims invalidated" vs. "claims sustained" split to report: claims 1–9 are all UNTESTED at the PTAB, and the defensive posture for a defendant is therefore "no IPR history to leverage or to be estopped by" — the patent has neither been hardened by surviving an IPR nor weakened by cancellation.

⚠️ Confidence caveat: This is an absence finding, stated at the confidence the sources support. If a proceeding was filed very recently (within the ODP ingest lag window), it would not appear. I found no evidence of one, but I cannot positively rule out an unindexed petition filed in the recent past. Do not treat "no proceedings" as a legal guarantee — pull the current PTAB E2E docket for the patent before relying on it in a filing.

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Proceedings

None. No proceedings to enumerate.

For completeness, here is what was checked and found negative:

• USPTO ODP structured "PTAB proceedings on file" block: no AIA trial proceedings returned.
• Web search for IPR/PGR/CBM referencing US 10,634,563: no petitions, institution decisions, FWDs, or terminations found. Search hits that mentioned "563" referred to unrelated patents (e.g., U.S. 9,917,563 and U.S. 8,090,862), not this patent.
• Federal Circuit / CourtListener: no appeal found referencing this patent number or US 2019/0086270 A1.

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Strategic summary

Claim status. All nine claims (1–9, with independent claim 1 and dependents 2–9) are UNTESTED — none has been canceled, disclaimed, or held unpatentable in an AIA trial. There is no narrowed claim set to hand a defendant and no cancellation to cite in a demand-letter defense. Note, however, that a defendant has other validity tools unaffected by PTAB history: §§ 101/102/103/112 in district court, inter partes reexamination, or a new IPR (if timely under § 315(b) and not barred by Fintiv-type discretionary considerations).

Estoppel landscape. § 315(e)(2) estoppel — the bar on raising in district court any ground a petitioner "raised or reasonably could have raised" in an IPR — does not apply to anyone here, because there has been no IPR. This cuts both ways:

• A defendant is not estopped from running any § 102/§ 103 art in litigation, and is free to file a first-chance IPR.
• But the patent owner also enjoys no benefit from prior adjudication, and there is no PTAB record (no claim constructions, no expert testimony, no institution findings) to borrow or attack.

Pattern signals. None present:

• No petitioner has filed once, let alone multiple times — there is no serial-petitioner pattern.
• No patent-owner PTAB appeals (there is nothing to appeal).
• No defensive aggregator (Unified Patents, RPX, etc.) appears in the chain. The assignee is AIST, a government research institute, not a monetizing NPE — that structural fact alone partly explains the absence of IPR activity, since well-asserted NPE patents typically attract IPRs while portfolio/never-litigated patents often do not.

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Recommended next steps

1. Confirm the negative directly. Because this is an absence finding, verify against live sources before relying on it: pull the PTAB E2E / Patent Trial and Appeal Board End-to-End system for Application No. 16/098,958 and Patent No. 10,634,563, and check the USPTO PatentCenter "Proceedings" tab. Web-search evidence is corroborating, not dispositive.

2. No FWD or CAFC opinion links are available to cite — none exists. Do not cite any proceeding number for this patent; none is real.

3. If you are a defendant being asserted against:

   • There is no PTAB history to anchor an IPR-estoppel or issue-preclusion argument.
   • Because no IPR was filed by anyone, § 315(b)'s one-year clock is measured from your own service date — you have a full year to petition if you choose; no prior petitioner has started it.
   • The patent is owned by a non-practicing research institute, so litigation-style defenses (damages, injunction posture) and validity challenges are on the table without any PTAB overlay.
   • Watch the current USPTO institution-policy environment (Director memorandum of 2025-10-16 centralizing institution decisions with the Director, plus the proposed rules restricting IPRs against patents that already survived a validity challenge): these may affect both your incentive to file and the likelihood of institution.

4. Flag for monitoring. If an IPR is later filed, the statutory timeline is: institution decision within 3 months of the patent owner's preliminary response (or ~6 months from filing if none), then a final written decision within 1 year of institution (§ 316(a)(11)), appealable to the Federal Circuit under § 319.

I'll research the assignment record for US patent 10,634,563 across USPTO Assignment Center and related sources.

Let me search for the specific assignment record and AIST's patent enforcement history.

Let me attempt to access the USPTO Assignment Center directly and verify the legal events.

Research note on sources

I attempted live queries against the USPTO Assignment Center endpoint and related dockets. I was not able to retrieve a reel/frame number or the correspondent of record for this patent within this session — the Assignment Center UI is not directly queryable via the tools available to me, and searches surfaced only derived records. I therefore report what is verifiable from the authoritative patent text plus the indexed legal-events record, and I explicitly flag anything I could not confirm rather than inventing reel/frame data.

The one assignment event indexed in the patent's legal-events record is: 2018-11-05 — Assigned to NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY (reassignment); Assignor: KOKUYAMA, WATARU. No other post-issuance transfer is recorded.

Inventors

• Unusual patterns: None. This is a single-inventor case, so there is no "inventors departing within 12 months" cohort to assess. There is no evidence of the inventor assigning away to a third party; the sole recorded transfer is inventor → AIST, the standard employer-assignment step.
• Because there is only one inventor and the assignee is his employer, the typical fire-sale precursor (a whole inventor team leaving right after filing) is not applicable here.

Original assignee

• Entity on the issued patent: National Institute of Advanced Industrial Science and Technology (AIST) — a Japanese national research and development institute (a government-established public body).
• Does it ship a product embodying the claims? No, not in a commercial-product sense. AIST is a research institute, not a commercial vendor; it does not market phase-measurement instruments under its own brand. The patent describes instruments (laser heterodyne displacement meters, phase-noise measurement devices) but AIST's role is R&D and publication/licensing, not product sales.
• Primary line of business: Publicly funded research and development across metrology, materials science, electronics, energy, and life sciences; AIST is one of Japan's largest public research organizations.
• Current status: Operating (AIST is an ongoing national research institute). No bankruptcy, dissolution, or acquisition is indicated.
• Patent status: Expired – Fee Related; anticipated expiration 2037-04-27 (per the patent's legal-status field). This is consistent with a research institute electing not to pay maintenance fees rather than with any assertion campaign.

Assignment timeline

Only one recorded assignment exists in the indexed legal-events record. I could not retrieve the reel/frame or the recorded correspondent; those fields are marked as not confirmed.

• Executed date: not retrieved / recorded 2018-11-05 — Reel not retrieved/NNNN (could not confirm; do not treat as verified)
  • Conveyance: Assignment (reassignment of interest)
  • Assignor: KOKUYAMA, Wataru (sole inventor)
  • Assignee: National Institute of Advanced Industrial Science and Technology (AIST)
  • Correspondent: Not retrieved in this session. (If confirmed, assess for recurrence — see signal 3; cannot be scored without the name.)
  • Context: Standard inventor-to-employer assignment; recorded around US national-stage entry (application US 16/098,958), not a fire-sale or transfer to an asserter.

No subsequent assignments, security agreements, mergers, changes of name, licenses, releases, or corrections are recorded. Per the task rules, this means the original assignee (AIST) still owns the patent as far as the record shows.

Timeline diagram

timeline
    title Ownership of US 10634563
    2016 : Priority date 2016-05-06
    2017 : PCT filing 2017-04-27
    2018 : Assignment to AIST recorded 2018-11-05
         : US national stage entered
    2020 : Patent issued 2020-04-28
    2037 : Anticipated expiration 2037-04-27

NPE / troll-pattern signals

1. Shell-entity transfer — not present. No assignment to any LLC/IP-holding/licensing entity appears in the record. The only transferee is AIST, a named national research institute with a real physical and institutional identity.

2. Known asserter in the chain — not present. Neither AIST nor inventor Kokuyama matches any public NPE/PAE directory (Acacia, Marathon, IV, Wi-LAN, Mosaid/Conversant, Vringo, Pendrell, etc.). No check against Unified Patents/RPX caselists returned this patent.

3. Repeat correspondent across the chain — not present / unclear. There is only one link in the chain, so "recurrence" cannot be scored. The correspondent name was not retrievable in this session; I am not inferring a finding from its absence.

4. Cascading transfers — not present. One assignment in the entire record; nothing chained, let alone through multiple LLCs in <24 months.

5. Pre-litigation transfer — not present. The lone assignment (2018-11-05) predates issuance (2020-04-28) by ~17 months and is an inventor-to-employer step, not a transfer to an assertion vehicle. No infringement suit naming this patent exists (consistent with the prior litigation section of this analysis).

6. Bankruptcy fire-sale — not present. No bankruptcy, Chapter 7/11, or asset-sale proceeding involving AIST appears.

7. Privateering — not present. No operating company transferred the patent to an NPE to assert on its behalf; the patent never left AIST.

8. Defensive aggregator — not present. The chain does not terminate at RPX, AST, LOT, Unified Patents, or OIN. The patent simply remains with its original research-institute owner.

Verdict

Insufficient data — but for a benign reason: the record contains only the original assignment (KOKUYAMA, Wataru → AIST, recorded 2018-11-05). Under the task's own definition, a chain consisting solely of the original assignment falls into this bucket, and I could not confirm reel/frame or correspondent fields to fully substantiate the chain. Substantively, every affirmative NPE signal is not present: the sole assignee is a Japanese public research institute that markets no products and has asserted nothing, and the patent is Expired – Fee Related with no litigation found. This is best read as a clean, non-asserted research-institute patent, not an NPE vehicle.

Verify at: USPTO Assignment Center — https://assignmentcenter.uspto.gov/ (search patent number 10634563), which is the authoritative source for the reel/frame and correspondent fields I could not retrieve here.

I'll research the prior art citations for US 10,634,563. Let me start with targeted searches of the patent's citation record.

Let me get the specific citation record from Google Patents and other patent databases.

Let me try to retrieve the patent's front-page citation list directly from the patent image/PDF source.

Prior Art Analysis — U.S. Patent No. 10,634,563 B2

Note on method and a transparency flag up front. I could not complete a live pull of the USPTO Patent Public Search / Patent Center "References Cited" field in this session (tool limit reached). The authoritative full patent text you supplied contains the specification-cited references (Patent Documents 1–4), and I retrieved the front-page citation table via the Google Patents / Justia mirror of the USPTO record (Justia: https://patents.justia.com/patent/10634563). Where I am describing the content/subject matter of an individual reference, that is my analytical characterization and I have flagged confidence levels — I did not read every cited reference in full. Treat the citation inventory as well-grounded and the per-reference subject-matter descriptions as requiring verification against the documents themselves before being used in a filing.

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1. The patent at issue (for anchor)

This matters for the anticipation analysis: because the application is post-AIA, the correct framework is §102(a)(1) (patents/printed publications publicly available before the effective filing date) and §102(a)(2) (U.S. patents/published applications with an earlier effective filing date), subject to the §102(b) grace-period/inventor-disclosure exceptions.

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2. Complete front-page citation inventory (as rendered in the USPTO record)

(a) U.S. Patent Documents (issue date shown)

(b) Foreign Patent Documents

(c) Non-Patent Citations

• V. Friedman, "A Zero Crossing Algorithm for the Estimation of the Frequency of a Single Sinusoid in White Noise," IEEE Transactions on Signal Processing, vol. 42, no. 6, June 1994.
• D. Grillo et al., "An Efficient Extension of the Zero-Crossing Technique to Measure Frequency of Noisy Signals," 978-1-4577-1772-7/12, ©2012 IEEE.
• C.T. Nguyen et al., "A new technique for rapid tracking of frequency deviations based on level crossings," IEEE Transactions on Power Apparatus and Systems, vol. PAS-103, no. 8, August 1984.
• H. Voelcker, "Zero-Crossing Properties of Angle-Modulated Signals," IEEE Transactions on Communications, June 1972, pp. 307–315.
• R.C. Wiley et al., "A Practical Procedure for Estimation of Instantaneous Frequency," IEEE Transactions on Instrumentation and Measurement, vol. IM-30, no. 1, March 1981.
• International Search Report (English) and Written Opinion dated July 11, 2017, from International Application No. PCT/JP2017/016764 (the instant application's own PCT).
• Extended European Search Report issued in EP Patent Application No. EP17792737.3, dated May 20, 2019.

(d) Specification-cited references (Patent Documents 1–4 in the description)

These are cited in the body of the patent, not necessarily in the front-page "References Cited" list. Three of the four also appear above as JP foreign documents:

⚠ Contradiction to flag: the specification expressly discusses JP 5468372 (Patent Document 3) as a phase-error detection/correction reference, but my retrieved front-page citation table does not list it. Either the mirror rendering is incomplete, or JP 5468372 was discussed by the applicant without being formally cited by the examiner. Do not assume it is examiner art. This should be resolved against the live USPTO file wrapper.

⚠ Also flag: the invented narrative references "PCT/JP/2015/081984 previously proposed by the inventors" — this corresponds to US 10,270,633 (Kokuyama), i.e., the inventor's own earlier work, which is in the citation list.

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3. Per-reference analysis and §102 mapping

Overarching conclusion, stated up front: No cited reference appears to disclose all elements of independent claim 1 — in particular the specific averaging formula U = C − (1/N)ΣG_j with G_j = N_j − F_j. That is consistent with the patent having issued over these references. The discussion below therefore identifies (i) which claims each reference is potentially relevant to under §102 only if it discloses the missing elements, and (ii) the specific claim element that the reference does not appear to supply. Claims 2–9 are dependent claims; I address them where the reference touches their added limitation.

3.1 U.S. patents

US 3,512,085 — Peterson et al., issued May 1970.
Description (moderate confidence): An early digital phase/frequency-measurement patent; the issuance era and the inventor/assignee context indicate counter- or zero-crossing-based phase measurement, cited as background.
§102 potential: Relevant, at most, to the broad concept of claim 1's "count processor … zero crossing detection count C." It would not, on its face, show the fraction processor or the Formula 1 averaging. Not an anticipation reference for claim 1 as a whole.

US 5,001,724 — Birgenheier, issued March 19, 1991.
Description (low–moderate confidence): A phase/time-interval measurement patent from the electronic-instrument (Tektronix/HP lineage) field; zero-crossing/counter-based measurement is the likely subject.
§102 potential: Background art going to claim 1's counting element. No indication it discloses the digital fraction-interpolation parameter G_j or the averaging formula.

US 6,522,983 — Dobos, issued February 18, 2003.
Description (low confidence): Instrumentation-domain patent (time-interval / modulation-domain measurement lineage) cited as background for measuring periodic-signal timing.
§102 potential: Background to the AD-conversion + timing-measurement aspects of claim 1. Does not appear to disclose the claimed fraction-processing parameter or Formula 1.

US 7,571,339 — Stimple, issued August 4, 2009. (Same inventor family as US 2007/0266275 below.)
Description (low–moderate confidence): Phase/frequency measurement instrumentation; cited for the general architecture of digital phase measurement.
§102 potential: Background to claim 1. No disclosure apparent of the G_j = N_j − F_j parameter or the Formula 1 averaging.

US 8,397,115 — Kimura, issued March 12, 2013.
Description (low confidence): Measurement/instrumentation patent; cited as background on phase or periodic-signal measurement.
§102 potential: Background to claim 1. No apparent disclosure of the claimed averaging computation.

US 10,270,633 — Kokuyama, issued April 23, 2019. (This is the inventor's own "previous proposal" — PCT/JP2015/081984.)
Description (high confidence — the instant specification describes it directly): A prior phase-measurement device by the same inventor in which, to obtain U, the averaging processor performs an integration operation on the output of the counter for each AD sampling. The specification states this imposes a heavy calculation load and that the present invention replaces it with the Formula 1 sum over G_j.
§102/§103 potential: This is the closest reference and the specification itself distinguishes it. It appears to disclose: AD conversion, a zero-crossing count, and a fraction/interpolation component — i.e., elements of claim 1. What it does not disclose is the claimed averaging performed as U = C − (1/N)ΣG_j with G_j = N_j − F_j; its averaging is a per-sample integration instead. Accordingly it is a candidate §102(a)(2) reference for claim 1 only to the extent claim 1's averaging limitation were read out — which it cannot be. More realistically it is §103 art.
⚠ Critical caveat: US 10,270,633 names the same inventor (Kokuyama). Under AIA §102(b)(2)(A), a disclosure that names the inventor and whose subject matter was obtained from the inventor is excepted from §102(a)(2) art. So even as §102(a)(2) art it is likely disqualified — and it is not §102(a)(1) art because it published (2019) after the 2016-05-06 priority date. Verify the exact inventorship/assignment chain before relying on it either way.

US 2005/0220242 — Ogasawara, published October 6, 2005.
Description (low confidence): Published application in the phase/frequency-measurement space.
§102 potential: §102(a)(1) art (pre-2016 publication). Background to claim 1. No apparent disclosure of the specific fraction parameter or Formula 1.

US 2007/0223634 — Haddad et al., published September 27, 2007.
Description (low confidence): Published application cited as background; instrumentation/signal-measurement subject matter.
§102 potential: §102(a)(1) art. Background to claim 1; no apparent disclosure of the claimed averaging.

US 2007/0266275 — Stimple, published November 15, 2007. (Publication counterpart/relative of US 7,571,339.)
Description (low–moderate confidence): Digital phase/frequency measurement instrumentation.
§102 potential: §102(a)(1) art. Background to claim 1; does not appear to disclose G_j or Formula 1.

US 2017/0324596 — Kokuyama, published November 9, 2017.
Description (moderate confidence): A Kokuyama publication in the same technical family as US 10,270,633.
§102 potential: Published after the 2016-05-06 priority date, so it can only be §102(a)(2) art (requiring an earlier effective filing date). If it is the pre-grant publication of US 10,270,633 (or another AIST/Kokuyama application obtained from the same inventor), the §102(b)(2)(A) inventor-disclosure exception likely removes it. Same substantive analysis as US 10,270,633: potentially relevant to claim 1's counting/fraction elements, but not the Formula 1 averaging.
⚠ Flag: I could not confirm in this session whether US 2017/0324596 is the publication of US 10,270,633 or a distinct application. Resolve this before using it as art.

3.2 Foreign patent documents

JP 2946675 — Japanese Patent No. 2946675, September 1999 (registration date; original publication earlier). (= specification "Patent Document 1")
Description (high confidence — described in the instant specification): A phase-difference measurement device for a laser heterodyne interferometer combining an up/down counter counting technique with a zero-crossing technique using a triangle wave generated from the input signal. The specification criticizes it because it requires a high-accuracy analog circuit to generate the analog triangle wave, making noise and analog drift irregular performance elements.
§102 potential: §102(a)(1) art. It maps to claim 1's count processor element and to the broad zero-crossing concept. It does not disclose a purely digital fraction processor producing G_j = N_j − F_j, nor the Formula 1 averaging. Notably, its analog-triangle-wave approach is the opposite of the claimed digital fraction approach — the examiner evidently did not treat it as anticipating.

JP 2003-188863 — Japanese Unexamined Patent Application Publication No. 2003-188863 (2003; the "December 2001" date as rendered conflicts with the number's 2003 publication year).
Description (low confidence): Japanese unexamined application cited as background on phase or periodic-signal measurement.
§102 potential: §102(a)(1) art. Background to claim 1. No apparent disclosure of the claimed fraction/averaging elements.
⚠ Flag: the date rendered in the source table ("December 2001") is inconsistent with a JP publication number of "2003-…". Verify the true publication date — it affects nothing about §102(a)(1) status (both pre-date 2016) but should be corrected for citation accuracy.

JP 2006-270372 — Japanese Unexamined Patent Application Publication No. 2006-270372, October 2006.
Description (low confidence): Background art on digital phase/periodic-signal measurement.
§102 potential: §102(a)(1) art. Background to claim 1; no apparent disclosure of the claimed elements.

JP 2007-232380 — Japanese Unexamined Patent Application Publication No. 2007-232380, September 2007. (= specification "Patent Document 4")
Description (high confidence — described in the instant specification): A frequency measurement method/device that performs an interpolation operation on amplitude values before and after the zero-crossing point, calculates the zero-crossing time, and derives frequency from the reciprocal of the difference in zero-crossing times; the real-time arithmetic operation is done on a DSP.
§102 potential: §102(a)(1) art. It is highly relevant to the fraction/interpolation element of claim 1 (the "fraction F_j … on the basis of the digital signals at sampling timings immediately before … and when the … zero crossing" concept). However, (i) it targets frequency, not phase, and (ii) it computes frequency from the reciprocal of a zero-crossing-time difference — it does not disclose the claimed averaging processor operating on count C plus accumulated G_j per Formula 1. So it does not appear to anticipate claim 1.

JP 2012-217121 — Japanese Unexamined Patent Application Publication No. 2012-217121, November 2012. (= specification "Patent Document 2")
Description (high confidence — described in the instant specification): A digital phase-difference measuring unit used inside a phase-locked loop; the input signal is AD-converted, a "sign clock" is generated, a phase comparing unit counts on a high-speed "count clock," and a phase correcting unit computes a correction value by linear interpolation for data before and after the zero-crossing point, summing the counter output and the correction value.
§102 potential: §102(a)(1) art. This is the most structurally analogous cited reference to claim 1:

• AD converter → claim 1 "AD converter."
• sign clock + zero-crossing → claim 1 "zero crossing specifying."
• phase comparing unit count → claim 1 "count processor … zero crossing detection count C."
• linear interpolation before/after zero crossing → claim 1 "fraction processor … fraction F_j."
• But it does not disclose (a) the parameter G_j = N_j − F_j using a zero-crossing detection number N_j within an averaging window N, or (b) the U = C − (1/N)ΣG_j averaging. It also measures phase against an internal clock (PLL), not absolute phase of an arbitrary periodic input — the specification criticizes it for this and for using multiple clocks. On that basis it does not anticipate claim 1 as a whole.

JP 5468372 — Japanese Patent No. 5468372 (= specification "Patent Document 3"; not in the retrieved front-page list)
Description (high confidence — described in the instant specification): A phase-error detection device that AD-converts an input, uses an equalization unit, a binarization unit, and an arithmetic operation unit computing a phase error by a metric operation; correction wraps the difference into ±180°.
§102 potential: §102(a)(1) art (if actually cited). Relevant to the general concept of detecting/correcting a phase error. The specification criticizes it because wrapping into ±180° loses a true phase difference exceeding ±180°. It does not disclose the claimed count/fraction/averaging structure. Verify whether it is actually of-record as art.

3.3 Non-patent literature

All five IEEE papers are §102(a)(1) printed publications (all pre-date 2016). They are background/theoretical art on zero-crossing frequency estimation and belong to the "zero-crossing technique" that the specification expressly acknowledges. Specifically:

None of these discloses the claimed digital fraction-processing parameter G_j = N_j − F_j or the Formula 1 averaging, so none anticipates claim 1. They are corroborating background that the zero-crossing technique was known.

The ISR/Written Opinion for PCT/JP2017/016764 and the EESR for EP17792737.3 are procedural documents about this application/family, not prior art. They are not §102 references and should not be cited as such. (Their value here is evidentiary: they show the search the examiner/ISA actually performed, which is why the JP references above appear.)

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4. Bottom-line §102 assessment

• No cited reference anticipates independent claim 1. The novelty-defining limitation — the averaging computation U = C − (1/N)∑_{j=1}^{L} G_j, with G_j = N_j − F_j and N_j the zero-crossing detection number within the averaging window N — is not disclosed by any reference in the list as described.
• Dependent claim 2 (correction of lost zero crossings when ΔG_j = G_{j+1} − G_j exceeds a threshold) is the claim for which the NPL noise-handling papers (Friedman 1994, Grillo 2012) are most plausibly relevant as background, but none appears to teach the claimed real-time ΔG_j-based lost-zero-crossing reconstruction. Same for claim 3 (the truncated counterpart).
• Closest art, for §103 rather than §102:

1. US 10,270,633 / US 2017/0324596 (Kokuyama) — same inventor; inventor-disclosure exception under §102(b)(2)(A) likely applies. Verify.
2. JP 2012-217121 — closest structural analogue (AD + sign clock + count + linear interpolation), but no G_j/Formula 1 averaging and PLL-referenced.
3. JP 2946675 and JP 2007-232380 — the counting-plus-zero-crossing and interpolation-of-zero-crossing-time disclosures, respectively, from which the claimed digital fraction/averaging structure is the point of departure.

• JP 5468372 is discussed in the specification but did not appear in my retrieved front-page citation list — resolve against the live record before treating it as examiner art.

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5. Recommended verification steps (because this is partly an absence/rendering finding)

1. Pull the USPTO Patent Public Search record for 10,634,563 and read the actual "References Cited" pane (U.S. Patent Documents, Foreign Patent Documents, Other Publications) to confirm the inventory above and to determine whether JP 5468372 is on the examiner-cited list.
2. Confirm US 2017/0324596's identity relative to US 10,270,633 (same family or not).
3. Fix the JP 2003-188863 publication-date anomaly.
4. Before relying on US 10,270,633 / US 2017/0324596 as art, verify the inventorship/§102(b)(2)(A) question, since both name Kokuyama.
5. For each reference you intend to assert, obtain and read the full document — the per-reference "brief descriptions" above are analytical characterizations, and several are flagged low-confidence.

Hard caveat: I did not verify the contents of every cited reference, and I could not run the live USPTO query in this session. Nothing here should be filed as a §102 anticipation chart without pulling each reference in full and confirming its disclosure against each claim element.

I'll verify the cited prior-art references against external sources before building the §103 analysis, since the "Prior Art section" here consists of the four Patent Documents listed in the patent's own BACKGROUND ART plus the inventors' earlier proposal.

Obviousness Analysis — U.S. Patent No. 10,634,563 B2 under 35 U.S.C. § 103

Analysis date: April 26, 2026
Governing statute: AIA § 103 (the application entered the U.S. as a § 371 national stage of PCT/JP2017/016764, filed 2017-04-27, claiming JP priority 2016-093389 of 2016-05-06 — i.e., post-AIA first-inventor-to-file). Prior art therefore is measured under AIA §§ 102(a)(1)–(2).

Scope note (carried forward, not repeated): The earlier sections of this file correctly flag that (i) claim 3 is truncated in the authoritative source, and (ii) claims 4–9 are unverified. This § 103 analysis therefore is built on claim 1 (full text available) and claim 2 (full text available), with claim 3 analyzed only to the extent its preamble + first clause are confirmed. I do not fabricate the remainder.

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1. The prior art of record

Per your instruction I used the Prior Art section of this page — i.e., the references listed in the patent's own BACKGROUND ART, which are the four "Patent Documents" (PD1–PD4) plus the inventors' earlier proposal. I verified each against independent sources:

Important correction/nuance to the prior file: the earlier "Patent summary" and "PTAB" sections treated US 10,270,633 only as a cross-reference. For § 103 purposes it is more than that — it is the single most on-point document, because the '563 specification itself frames the invention as an improvement on that very proposal ("In order to calculate the value of U with a high degree of accuracy … a strong calculation load is imposed to an FPGA, and the reduction becomes a problem. According to Formula 1 … it is possible to remarkably reduce the calculation load as compared with the previous proposal."). That admission is analyzed below, but it must not be assumed to be citable art (there is a serious common-ownership/grace-period obstacle).

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2. Elemental decomposition of the challenged claims

Claim 1 (independent)

Claim 2 (dependent on 1) — lost zero-crossing correction

Correcting unit; when ΔG_j = G_{j+1} − G_j exceeds a threshold, estimate the lost crossing count, add it to C, and estimate the missing G_j from the neighboring G values.

Claim 3 (dependent on 1) — excess/false zero-crossing correction (preamble + first clause only)

Same correcting-unit architecture and same ΔG_j threshold test, but for extra detections: subtract from C and subtract a G_j value.

Observation: Limitations 1A–1C are, in substance, the disclosure of PD2, and the combination of integer counting with sub-sample fractional measurement is the express teaching of PD1. The point of novelty over the art of record resides almost entirely in 1D (and its G_j parameterization in 1C) — i.e., the specific arithmetic combination over an averaging window.

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3. Grounds of rejection under § 103

Ground A (primary) — Claim 1 obvious over PD2 in view of PD1 and PD4

The mapping:

• 1A — PD2: "the input signal is first digitized by the AD converter." Anticipated.
• 1B — PD2: the "sign clock" indicates whether the digital input value is positive or negative (a sign-change / zero-crossing detector), and the phase-comparing unit counts using the count clock. That is limitation 1B (count processor + counting of crossings).
• 1C — PD2: the phase-correcting unit "calculates a phase correction value through a linear interpolation operation for data before and after a zero crossing point." PD4 independently teaches interpolating the amplitude values immediately before and after the zero-crossing point to fix the sub-sample crossing position. Thus the fraction F_j and the crossing position within the window are supplied by PD2/PD4. Re-expressing that fraction as G_j = N_j − F_j is a mere change of variable / algebraic bookkeeping — the underlying physical quantities (sample index N_j, interpolated fraction F_j) are the same ones PD2/PD4 already compute.
• 1D — the only true gap. PD2 discloses summing the counter output and the correction value ("calculates a sum of an output value of the phase comparing unit and the phase correction value"), and averaging of count values to improve resolution is conceded by the patent to be a known technique ("a technique of averaging a plurality of count values is often used"). Combining the per-crossing fractional corrections with the integer count over a fixed N-sample window — with the window chosen to set the output rate at f_ADC/N — is the predictable result of applying routine averaging (well-known in frequency counters/gate-time measurement and expressly acknowledged in the '563 BACKGROUND) to the PD2 architecture.

Motivation to combine (why a POSITA would do it):

1. PD1 — express teaching/suggestion. PD1 is in the same field (heterodyne interferometer phase-difference measurement) and is built on precisely the idea of combining a coarse integer count with a fine intra-fringe (fractional) measurement to obtain high-resolution phase difference. The '563 BACKGROUND itself states the motivation as settled art: "integration of the counting technique capable of coping with the high-speed phase change and the zero crossing technique capable of coping with the high accuracy phase measurement is extremely effective." That is, in effect, an admission of a known motivation to combine the two techniques.
2. PD2 — the digital implementation. PD1 achieves the fraction with an analog triangle wave and an analog multiplexer; the '563 BACKGROUND criticizes that an "analog circuit is necessary" and "noise and change in characteristic of the analog part are irregular elements." Substituting PD2's digital AD-convert + sign-clock + linear-interpolation front end is the classic substitution of one known element for another to obtain the predictable advantage of eliminating analog drift (KSR; In re Keller, 642 F.2d 413). A POSITA would have found it obvious to digitize PD1's analog triangle-wave fraction measurement in the manner of PD2.
3. PD4 — the interpolation for the sub-sample crossing. PD4 supplies the specific technique (linear interpolation of the samples immediately before/after the crossing to obtain the exact crossing position) that the '563 fraction processor recites. PD4 is in the same field (periodic-signal frequency/phase metrology) and its combination with PD2's count-and-correct architecture is a mere juxtaposition of known elements, each performing its own function (KSR; In re Merck).
4. Averaging — design incentive / obvious to try. Averaging N samples to (a) reduce noise and (b) improve resolution is ubiquitous in the counting art and is conceded in the patent's own BACKGROUND. Choosing the window to yield equal output intervals at f_ADC/N is a design choice driven by the acknowledged demand in digital signal processing for a constant output rate — which the '563 BACKGROUND itself says is desirable ("it is desirable to calculate a result at equal time intervals even when the frequency of the input signal greatly varies"). Where the specification identifies the problem and the prior art supplies the mechanism, the solution is obvious.

KSR rationales engaged: (A) combining prior-art elements according to known methods to yield predictable results; (B) simple substitution of a known digital element for a known analog one; (C) use of a known technique (averaging) to improve a similar device in the same way; (D) applying a known technique to a known device ready for improvement; (E) obvious to try — a finite, predictable set of ways to average the count and fraction; (F) design incentive / market pressure for real-time equal-interval output.

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Ground B (alternative primary) — Claim 1 obvious over PD1 in view of PD2 and PD4

If PD2 is treated as the architecture and PD1 as the motivation, the combination is equally supported: PD1 supplies the point of departure (counting + intra-fringe fraction in a heterodyne interferometer), PD2 supplies the digital AD/sign-clock/linear-interpolation implementation, and PD4 supplies the precise pre/post-crossing interpolation for the fraction. This ordering is more faithful to the actual chronology (PD1 is the oldest and the most field-specific) and to the specification's own narrative, which treats PD1 as the closest "counting + zero-crossing" art.

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Ground C (the formula, limitation 1D) — routine optimization / obvious efficiency modification

Even if PD1–PD4 are found not to literally reach U = C − (1/N) ΣG_j, the expression is:

• a purely mathematical combination of quantities the art already produces (integer count C; per-crossing positions N_j and fractions F_j); and
• attributable to a recognized, admitted motivation: the '563 specification expressly says the new formulation "remarkably reduce[s] the calculation load" relative to the previous proposal, which performed an integration per AD sample. An improvement whose stated benefit is reduced computational burden is a paradigm case of an obvious modification (In re Applied Materials; KSR — "design incentives"; see also the Federal Circuit's treatment of efficiency-motivated algorithmic changes).

Motivation: (i) The prior device's per-sample integration of a wide-bit-width value "imposes a strong calculation load … to an FPGA," and reducing FPGA load is a routine engineering objective; (ii) the reformulation is applied to a known device (the sibling architecture) ready for improvement; (iii) the result (the same phase value, computed more cheaply) is predictable. A POSITA would have been motivated to rearrange the averaging arithmetic to avoid a per-sample multiply-accumulate — that is exactly the kind of "predictable variation" KSR holds obvious.

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Ground D — Claims 2 and 3 obvious over PD3 in view of PD1/PD2

• Claim 2's architecture — a correcting unit that tests a monitored phase-related quantity against a threshold/range and corrects when the test fails — is the express disclosure of PD3 ("determines whether the phase error … falls within a range determined from past phase errors … when the phase error is out of the range, [corrects]"; US 2010/0169730 ¶¶0103–0109). PD3 thus teaches the generic anomaly-detection-and-correction module recited by claims 2–3.
• Adapting that module to the lost/excess crossing problem in a counting-based phase meter is an obvious application of the known correction concept to the known PD1/PD2 measurement, because lost fringes (cycle slips) from weak return signals are a notorious, well-known problem in heterodyne interferometry — precisely PD1's field. The '563 specification's own justification is mathematical and routine: it relies on the fact that two crossings are lost as a set, and on the approximation G_k + G_{k+1} = G_{k−1} + G_{k+2}, so that the missing G can be interpolated from its neighbors. Interpolation from neighboring samples is exactly what PD4/PD2 already teach.
• The threshold is conceded by the applicant to be a design choice ("a value decided using an average frequency of the input signal and may be assigned a fixed value as an initial setting or may be decided by multiplying a long-time average of ΔG_j by an appropriate coefficient").
• Claim 3 is the mirror image of claim 2 (subtract instead of add, for over-detection). Once claim 2's correction architecture is obvious, claim 3 is an obvious reversal/duplication of the same operation for the opposite sign of the same error.

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4. Motivation-to-combine — consolidated statement

A person of ordinary skill (a metrology/FPGA-digital-design engineer with a working knowledge of heterodyne interferometry and phase-locked loops) at the 2016 priority date would have been motivated to combine PD1, PD2, PD4 (and PD3 for the correction claims) for the following reasons, each supported by the references themselves or by express admissions in the '563 specification:

1. Same field, same problem. All of PD1–PD4 address measuring the phase/phase-difference/frequency of a periodic (usually sinusoidal) signal; combination is within the field of endeavor and reasonably pertinent to the problem (KSR; In re Bigio is inapposite because the field is the same).
2. PD1 gives the "why." PD1 embodies the recognized synergy of coarse counting + fine fractional measurement; the '563 BACKGROUND concedes this synergy is "extremely effective" — a virtual admission of the motivation.
3. PD2 gives the "how" (digital). PD2 supplies AD conversion, sign-based crossing detection, a counting unit, and linear-interpolation phase correction — i.e., the very architecture limitations 1A–1C recite.
4. PD4 gives the "exactly how" for the fraction. PD4's pre/post-crossing interpolation yields the sub-sample crossing position that the fraction processor computes.
5. Averaging gives the "over what window." Averaging over a fixed sample count is old, is conceded as old, and yields the acknowledged desideratum of an equal-interval output at f_ADC/N.
6. PD3 gives the "error handling." PD3 supplies the threshold/range check-and-correct module that claims 2–3 recite.
7. Predictability. The resulting device performs the same function (phase measurement) with the expected improvements (higher resolution, lower computation), and the modifications involve no change in the principle of operation — the hallmark of an obvious combination.

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5. Anticipated rebuttals (what the patent owner will argue) and the counter-rebuttal

A complete § 103 assessment must state the counter-case:

Secondary-consideration posture: I found no evidence (consistent with the earlier litigation section of this file) of commercial success, licensing, industry praise, copying, or failure-of-others tied to this patent; the patent is marked Expired – Fee Related and appears never to have been asserted. Absent such evidence, secondary considerations likely carry little weight.

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6. Two structural obstacles a challenger must confront (flagging honestly)

(a) § 101 overlay. Limitations 1D (and much of 1C) are, at bottom, an arithmetic formula. A challenger's § 103 case that leans heavily on "the formula is routine math" simultaneously exposes the claim to an Alice/Mayo § 101 attack (abstract idea + generic processors). The patentee's best § 101 defense would be that the claims integrate the formula into a practical measurement device (AD converter + hardware processors) producing a real-time, equal-interval physical measurement — i.e., an Enfish/McRO-type improvement in measurement technology. This interplay is strategic: pressing the "the math is obvious" theory too hard strengthens the § 101 theory but not necessarily the § 103 theory, and vice versa. I flag this rather than resolve it.

(b) The best reference may be inadmissible as art. The single most on-point document — US 10,270,633 / EP 3 220 545 A1 (the inventors' prior proposal, PCT/JP2015/081984) — is commonly owned by AIST with the '563 patent. Because both were AIST-owned no later than the '563 effective filing date, the AIA § 102(b)(2)(C) common-ownership exception likely removes it as § 102(a)(2) art, and the inventor's own disclosure is further subject to the § 102(b)(1)(A) grace-period exception. I confirmed the family relationship via the EP publication's claims (EP 3 220 545 A1) and US 10,270,633. Consequence: a defendant cannot safely premise a § 103 rejection on '633 alone; the case must be built on PD1–PD4 (all clearly § 102(a)(1) art). The '633 family remains usable as evidence of the state of the art and of the applicant's own admissions about the prior architecture and the load-reduction motivation.

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7. Conclusion

Bottom line: Claim 1 is highly vulnerable to a § 103 rejection built on the four Patent Documents of record, because every functional element is taught or suggested by PD1 (count + intra-fringe fraction), PD2 (AD + sign-clock counting + linear-interpolation correction), and PD4 (pre/post-crossing interpolation), and the only genuinely distinguishing feature — the averaging formula and its G_j parameterization — is a routine, admitted calculation-load-reduction reformulation of the same quantities. The chief practical obstacles to a challenger are (i) the § 101/§ 103 tension around the formula and (ii) the fact that the closest document ('633/EP 3 220 545) is probably excepted prior art under AIA §§ 102(b)(1)(A)/(b)(2)(C), so the rejection must be built on PD1–PD4 alone.

Residual uncertainties: I could not verify the full text of claims 3–9; my § 103 conclusions for claims 4–9 are therefore withheld rather than estimated. The threshold values, window-sizing, and interpolation specifics recited in the dependent claims are, on the record available, matters of design choice — but that judgment should be re-confirmed against the full claim set before reliance.