Invalidity dossier
US 10496554
System on chip and method of executing a process in a system on chip
Current assignee: NXP USA Inc
Added 9/23/2026, 2:09:54 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview: US10496554B2
Title: System on chip and method of executing a process in a system on chip
Patent number: US10496554B2 (application US14/194,862; pre-grant publication US20150248358A1)
Current assignee (as listed): NXP USA Inc; original assignee NXP USA Inc, with an early assignment to Freescale Semiconductor, Inc.
Key dates from the supplied text:
- Priority/filing date: 2014-03-03
- Pre-grant publication: 2015-09-03
- Grant/publication of US10496554B2: 2019-12-03
- Legal status: Active, adjusted expiration 2035-01-16 (status is an assumption, not a legal conclusion)
Inventors: Michael Johnston, Alan Devine, Alistair Paul Robertson, Manfred Thanner
Purpose / plain-language scope (from the definitions in the excerpt): The patent concerns a system on chip — described as a computer on a single semiconductor chip — comprising a processing unit that reads executable instructions from a program memory unit and executes them. The processing unit may have one or more processor cores operating in parallel; the program memory unit may be programmable, non-programmable (hardcoded), or both. The text also distinguishes a program (a passive collection of instructions) from a process (the actual execution of those instructions, possibly with multiple concurrently executing threads), and notes the system may include a data memory unit, which may share a single physical memory with the program memory unit.
Classification highlights: G06F12/14 and G06F12/1458–1475 (memory protection, key-lock mechanisms), G06F21/52 and G06F21/71 (platform integrity during program execution; secure computing), and G06F15/7807 (system on chip).
Source: https://patents.google.com/patent/[US10496554](/patent/US10496554)/en
What the excerpt does not establish: The claims are absent, so the precise scope of protection is not shown. It does not describe the invention's distinguishing features over prior art, the detailed embodiments, or the specific mechanism by which memory-region activity counts are used — beyond the prior-art keywords ("memory," "activity count," "memory region," "count," "chip"). It also does not establish litigation, validity, or ownership conclusions.
Generated 10/1/2026, 9:52:30 PM
Cases on file (0)
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Litigation summary
Past and pending lawsuits — plaintiffs, defendants, jurisdictions, outcomes, and notable rulings.
Proceedings on file (0)
All PTAB activity →AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.
No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.