US 10346087

The first search returned an unrelated Apple design patent (D593,087), not our target. Let me run additional targeted searches.

Bibliographic data is confirming. Now let me check for any CAFC 2026 litigation involving this specific patent.

I have gathered the available information. Here is my summary.

US Patent 10346087 — Summary

Note on search results: The USPTO/Google Patents search confirmed the bibliographic record for US10346087B2 (application US15/678,759). A search for CAFC 2026 dockets involving this patent returned no results — I found no evidence of any Federal Circuit appeal, PTAB/IPR, or other 2026 litigation involving patent 10346087. (One search hit was for an unrelated Apple design patent, D593,087 — not this patent.)

Bibliographic Data

• Patent number: US10346087B2
• Title: Apparatus for outputting internal state of memory apparatus and memory system using the apparatus
• Assignee: [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)
• Inventors: Seong-Hoon Woo; Hak-Sun Kim; Kwang-Jin Lee; Su-Chang Jeon
• Filing date: August 16, 2017 (US Application No. 15/678,759)
• Priority date: August 16, 2016 (Korean Application No. 10-2016-0103752)
• Issue date: July 9, 2019
• Status: Active; anticipated expiration 2037-08-16
• Classifications (selected): G11C16/00 (erasable programmable ROMs); G11C7/10, G11C7/1051, G11C7/1063 (I/O data interfaces, data output circuits, control signal/status output circuits); G06F3/06, G06F13/16

Abstract

An apparatus for outputting an internal state of a memory apparatus and a memory system using the apparatus are provided. The apparatus includes a state signal generating circuit that generates a first signal indicating an internal operation state of the memory apparatus, and a state signal output control circuit that receives the first signal and outputs a second signal to an output pad based on a chip enable signal or an initially set function command, or both. The first signal indicates one state from among two states and the second signal indicates one state from among three states.

Plain-Language Overview of the Independent Claims

Caution: the full, formally numbered claim text was not available in the source material I retrieved. The following is based on the machine-extracted claim summaries (Google Patents "Definitions" section) and should be verified against the issued patent before relying on it in litigation or prosecution.

The patent appears to contain three independent claims:

1. Apparatus claim (state-signal output apparatus): An apparatus for a memory apparatus comprising (a) a state signal generating circuit that generates a first signal indicating an internal operation state, and (b) a state signal output control circuit that receives the first signal and outputs a second signal to an output pad based on at least one of a chip enable signal and an initially set function command (e.g., a "CE reduction command"). The first signal indicates one of two states (e.g., ready/busy), while the second signal indicates one of three states (e.g., logic 0, logic 1, and high-impedance/Hi-Z). In plain terms: the memory chip only drives its ready/busy pin when selected by chip-enable, and otherwise floats the pin to high impedance, creating a tri-state output that allows multiple chips to share one controller pin.

2. Memory-system claim (three logic levels): A memory system with a plurality of memory chips, each having at least one first state output pin, and a memory controller having a first state input pin connected to the chips' state output pins in a wired-AND configuration. The controller transmits a chip enable signal and/or an initially set function command to the chips. Each chip outputs a first state signal having one of three logic levels according to its first internal operation state, based on the chip enable signal and/or the initially set function command. In plain terms: all chips share a single status pin on the controller; because only the chip-enable-selected chip drives the line while others are Hi-Z, the controller can tell which specific chip is busy/ready.

3. Memory-system claim (enable/disable response): A memory system with a plurality of memory apparatuses, each having a first state output pin, and a memory controller coupled to those pins and configured to transmit a chip enable signal and/or an initially set function command to each chip. In response to receiving an enable signal, the memory apparatus outputs a first state signal reflecting its internal operation state to its state output pin; in response to receiving a disable signal, the memory apparatus outputs a high-impedance state. In plain terms: this claim captures the gating behavior — the chip drives its status pin only when enabled and releases it (Hi-Z) when disabled, which is what enables wired-AND sharing of a single controller status pin while still allowing per-chip state identification.

Uncertainty / Caveats

• Claim numbering and exact claim language are not verified; the three independent claims above are reconstructed from Google Patents' machine-extracted definitions and match the specification's disclosed three inventive aspects (apparatus claim; system claim with three logic levels; system claim with enable/disable Hi-Z behavior). Confirm against the issued patent PDF before citing in any formal analysis.
• No CAFC 2026 docket activity was found for this patent. If you need a definitive clearance, I'd recommend checking the USPTO Patent Center and PACER/CAFC docket search directly, since my search coverage of 2026 dockets may be incomplete.

Based on the searches I was able to run, I found no known litigation involving US Patent 10,346,087 ([[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.), "Apparatus for outputting internal state of memory apparatus and memory system using the apparatus," granted July 9, 2019, inventors Seong-Hoon Woo, Hak-Sun Kim, Kwang-Jin Lee, and Su-Chang Jeon).

Search results and caveats

• A general search for "10346087" litigation surfaced only a PlainSite docket for USPTO Patent Application No. 10,346,087 (applicant Kikuchi Shinichi, "Information recording/reproducing apparatus") — that is an application number for an unrelated patent application, not the granted US patent 10,346,087 at issue. I excluded it as non-matching.
• Searches combining "10346087" with "Samsung," "lawsuit," "v./vs.," "complaint," and "defendant" returned only inventor/patent-leaderboard pages and unrelated NAND ready/busy patents (e.g., US 9,093,132, US 8,179,732, US 2013/0128675, CN108335711B). None of these reference litigation over US 10,346,087.
• No PACER, CAFC, ITC, PTAB/IPR, or Unified Patents caselist results referencing US 10,346,087 were located in the searches performed.

Conclusion

To my knowledge and based on the available search results, US Patent 10,346,087 is not currently involved in any known litigation — no district court cases, ITC investigations, or PTAB proceedings naming this patent were identified.

Important caveats:

• This patent is owned by Samsung Electronics and is comparatively young (granted 2019); large operating companies like Samsung frequently hold patents without asserting them, so the absence of litigation is plausible but unconfirmed.
• Patent-litigation dockets are not fully indexed by general web search. To verify with confidence, I would recommend checking:
  • PACER (federal district court dockets),
  • Unified Patents litigation portal (https://portal.unifiedpatents.com/litigation/caselist),
  • RPX / DocketNavigator (subscription databases),
  • PTAB (USPTO) for IPR/PGR proceedings, and
  • USITC for Section 337 investigations.
• If any of those sources are accessible to you, a search there for "10,346,087" (or the parent application family, including continuations US 11,003,382, US 11,847,339, and US 12,189,976) would be the definitive check.

Proceedings overview

There are zero AIA trial proceedings on file for US Patent 10,346,087 — no IPRs, no PGRs, no CBM reviews — as confirmed by the USPTO Open Data Portal (no AIA trial proceedings returned for this patent as of the most recent ingest) and independently corroborated by web searches for PTAB dockets, Final Written Decisions, and CAFC appeals naming the patent or its parent family (KR 10-2016-0103752; continuations US 11,003,382, US 11,847,339, US 12,189,976). The bottom-line defensive posture: there is no PTAB record to help you or hurt you — every claim remains untested before the Board, and the patent's validity has never been adjudicated in an AIA trial.

No per-proceeding sections follow because there are no proceedings. I will not invent proceeding numbers, judge panels, or decisions.

Strategic summary

Claim status: all claims UNTESTED, none CANCELED, none SUSTAINED. US 10,346,087 issued 2019-07-09 and has never been challenged at the PTAB. Its three independent claims (the state-signal output apparatus claim; the memory-system claim reciting three logic levels on a wired-AND state input pin; and the memory-system claim reciting enable-driven output versus disable-driven high-impedance) — and all dependent claims — remain in force exactly as granted. No IPR institution decision, no Final Written Decision, and no PTAB-issued certificate of cancellation exists for this patent. The patent's "Active" status (anticipated expiration 2037-08-16) is consistent: nothing has narrowed or invalidated any claim administratively.

Estoppel landscape — a blank slate, which cuts both ways. Because no IPR/PGR has ever been instituted on this patent, no petitioner is estopped under 35 U.S.C. § 315(e)(2) (or the PGR analogue, § 325(e)(2)), and no prior-art ground has been "used up." For a defendant currently facing assertion of 10,346,087, all § 102 and § 103 grounds based on patents and printed publications remain fully available for a first-filed IPR petition — including art the patent owner may have distinguished during prosecution, which the Board could still weigh under § 325(d) discretion. One structural caution: this patent claims priority to August 16, 2016 (Korea), so a § 102(a)(2) analysis turns on that date, and any challenger must clear the one-year bar from service of an infringement complaint (35 U.S.C. § 315(b)). Because this is a memory-interface/ready-busy signaling patent in a crowded art (G11C7/1063 — "control signal output circuits, e.g., status or busy flags"), well-chosen NAND/status-pin prior art from the mid-2010s is a plausible IPR target — but nobody has yet brought one.

Pattern signals — none. There is no repeat petitioner, no defensive-aggregator chain (Unified Patents, etc.), no patent-owner aggressiveness at the Board (because there was nothing to defend), and no Federal Circuit appeal. The patent owner, Samsung Electronics, holds the patent without any recorded PTAB enforcement history. Notably, the patent family has been kept alive through three continuations (US 11,003,382B2; US 11,847,339B2; US 12,189,976B2, issued 2025-01-07), showing the family is commercially maintained — but maintenance is not assertion, and no litigation or PTAB activity naming any family member surfaced in my searches. The absence of IPRs is itself informative: well-asserted patents in this space typically attract challenges within a few years of grant; the fact that this patent has gone seven years post-filing (five-plus years post-issue) without a single petition suggests either (a) it has not been aggressively enforced, or (b) potential challengers have concluded the art is not favorable.

Recommended next steps

• If you are a defendant facing assertion of 10,346,087 today: Do not rely on any PTAB record — there is none to cite. The absence of IPRs means no claim has been canceled, so every infringement theory the plaintiff can plead is technically "alive." Your validity play must be built from scratch. If you intend to file an IPR, move promptly: the § 315(b) one-year bar runs from service of the complaint, the petition is subject to the Director's discretionary-denial framework (including parallel-litigation considerations), and you should prepare a § 325(d) response for any art already of record in prosecution. § 101/§ 112 challenges are unavailable in IPR and would need to be raised in district court.
• Verify the zero-proceeding finding before relying on it formally. The ODP ingest and my web searches returned nothing, but PTAB dockets are not exhaustively indexed by general web search. Run the definitive checks: USPTO PTAB E2E (search "10,346,087" and the application number 15/678,759), Patent Center, and Unified Patents' litigation portal (https://portal.unifiedpatents.com/litigation/caselist). Also check for ex parte reexamination (EPRx) — EPRx does not appear on AIA-trial dockets and could exist without surfacing in the ODP AIA feed; a search of USPTO's reexam database would rule it out.
• Monitor the family. The continuation lineage (US 11,003,382 → US 11,847,339 → US 12,189,976, the last issuing 2025-01-07) means a challenger must decide whether to attack the parent (10,346,087), a continuation, or all of them — a petition against the parent alone will not estop or bind the continuations' claims. Any IPR strategy should map the family's claim sets before filing.
• If you are the patent owner (Samsung or a licensee): the clean PTAB slate is a strength — no claim has been narrowed, and no FWD exists that a future defendant could invoke. But it also means the patent has not been "hardened" by surviving review; expect that a first serious assertion will draw a first IPR. Consider whether any claim amendments or continuation filings (already underway through 2025) should be used to position fallback scope before a challenge lands.

Bottom line: Zero PTAB proceedings. No claims invalidated, no claims sustained, nothing settled, nothing denied. The patent is untested, fully in force, and — for a defendant — the validity fight has not yet been fought anywhere.

Inventors

All four named inventors were employees of [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.) at the time of filing, and all four executed the recorded assignment to Samsung:

• Seong-Hoon Woo — Samsung Electronics (listed residence: Hwaseong-si, KR)
• Hak-Sun Kim — Samsung Electronics (Suwon-si, KR)
• Kwang-Jin Lee — Samsung Electronics (Hwaseong-si, KR)
• Su-Chang Jeon — Samsung Electronics (Seoul, KR)

Unusual-pattern check: no red flag. The same four inventors appear on the continuation family (US 2021/0294517 A1, filed 2021-04-15), which indicates continued employment at Samsung well past the 12-month post-filing window. There is no evidence of a mass inventor departure preceding a portfolio transfer.

Original assignee

• Entity on the issued patent: Samsung Electronics Co., Ltd. (Suwon-si, KR)
• Line of business: Global semiconductor and consumer-electronics operating company; one of the world's largest manufacturers of NAND flash memory, DRAM, and SSDs.
• Product embodiment: Samsung ships NAND flash memory devices and SSD controllers whose ready/busy (RnB) signaling and chip-enable-based output gating fall squarely in the technology space of the claims. I cannot confirm a specific SKU embodies the exact claims without teardown-level evidence, but the claimed tri-state RnB scheme is consistent with Samsung's memory product line.
• Current status: Operating and active; Google Patents shows the patent Active with anticipated expiration 2037-08-16.

Assignment timeline

I was unable to retrieve the exact reel/frame numbers or correspondent of record from the USPTO Assignment Center via the searches available to me. The following is what is verified from the patent record and Google Patents legal events; the reel/frame, correspondent name, and any other recordings should be confirmed directly at https://assignmentcenter.uspto.gov/ before relying on this in a formal analysis. I have not fabricated any reel/frame numbers.

• 2017-08-16 (executed and recorded same day as the US filing, 2017-08-16) — Reel/frame: not retrievable from available sources
  • Conveyance: Assignment of Assignors' Interest (see document for details)
  • Assignor: Su-Chang Jeon; Hak-Sun Kim; Kwang-Jin Lee; Seong-Hoon Woo (all four inventors)
  • Assignee: Samsung Electronics Co., Ltd.
  • Correspondent: not retrievable from available sources
  • Context: Standard employment/filing-day assignment from inventors to their employer, coincident with filing of application 15/678,759.

No post-issuance assignments were found. Google Patents' legal-event feed for US10346087B2 shows only the single 2017-08-16 assignment; the subsequent events are continuation filings (US16/503,116 → US11003382B2; US17/231,734 → US11847339B2; US18/506,293 → US12189976B2), all of which name Samsung Electronics Co., Ltd. as applicant/assignee. The absence of post-issuance recordings is itself a finding: the original assignee, Samsung, still owns the patent.

Timeline diagram

timeline
    title Ownership of US 10346087
    2016 : Korean priority filing
    2017 : US application filed
         : Assigned to Samsung Electronics
    2019 : Patent issued
    2021 : Continuation filed by Samsung

NPE / troll-pattern signals

1. Shell-entity transfer — Not present. The only recorded assignment is from the four inventors to Samsung Electronics Co., Ltd., a publicly traded operating company. No LLC, IP-holding, or licensing entity appears anywhere in the chain.

2. Known asserter in the chain — Not present. No Acacia, Marathon, IV, IPNav, Wi-LAN, Conversant/Mosaid, Vringo, Pendrell, Innovatio, MPHJ, Lumen View, Round Rock, Document Generation Corp, or Spangenberg entity appears in any recorded assignment or legal event for this patent.

3. Repeat correspondent across the chain — Unclear. Only one recording exists, so there is no chain in which recurrence could be assessed. The correspondent of record for the single 2017-08-16 assignment could not be retrieved from the searches available to me.

4. Cascading transfers — Not present. There is exactly one assignment; no chained LLC transfers exist.

5. Pre-litigation transfer — Not present. The only assignment predates issuance by ~2 years and coincides with filing (normal employer assignment). No infringement litigation naming this patent was identified in prior analysis, so there is no suit against which to measure a transfer.

6. Bankruptcy fire-sale — Not present. Samsung Electronics has not filed bankruptcy; no estate or trustee appears in the chain.

7. Privateering — Not present. No transfer from Samsung to any third-party NPE appears; Samsung itself holds the patent.

8. Defensive aggregator (anti-NPE) — Not present. The chain terminates at Samsung, an operating company — not RPX, AST, LOT Network, Unified Patents, or OIN.

Verdict

Insufficient data (with a strong ownership-side observation).

The chain contains only the single filing-day assignment from the four inventors to Samsung Electronics Co., Ltd. (recorded 2017-08-16), and the continuation family confirms Samsung has held the patent continuously through at least 2023. No NPE signals are present, and no litigation was identified, so I cannot label this "operating-company assertion" in the absence of any evidence of enforcement — but the record affirmatively shows an operating company, not a licensing entity, as current owner. For verification of the reel/frame and correspondent for the one recorded assignment, search the patent number at https://assignmentcenter.uspto.gov/ (the single recording is the 2017-08-16 assignment of inventors' interest to Samsung).

I'll search for the citations listed on US Patent 10346087 and related prior art.

The initial searches didn't surface the citation list. Let me run more targeted searches to identify the references cited on the face of US10346087.

I found that US8429313B2 ("Configurable ready/busy control") is listed on Google Patents as related to US10346087. Let me dig deeper to identify the full citation list on the face of US10346087.

I've reached the limit of my available search steps. Here is my analysis based on the information I was able to retrieve and verify, with clear flags on what could not be confirmed.

Prior Art Analysis — US Patent 10346087B2

Methodological note and caveats

I was able to confirm two prior-art references in the citation network of US10346087B2 through Google Patents search results, but I could not retrieve the complete, USPTO-verified "Patent Citations" section from the face of the patent within the search steps available. The claims themselves are also not available in formally numbered form in my source material (the earlier summary flagged this; the independent claims are reconstructed from Google Patents' machine-extracted "Definitions" section). Accordingly:

• The two references below are confirmed as related/cited references in the Google Patents family data, but a full anticipation opinion for every dependent claim cannot be responsibly rendered without (a) the complete USPTO citation list and (b) the full claim text.
• Before relying on this analysis in litigation or prosecution, verify the complete citation list via USPTO Patent Center (patent US10346087) or the Google Patents "Citations" tab for US10346087B2.

Confirmed prior-art references

1. US 8,429,313 B2 — "Configurable ready/busy control"

• Assignee: [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)
• Priority date: May 27, 2004
• Publication/grant: Granted April 23, 2013 (application filed May 27, 2004)
• Status relative to US10346087: Prior art under pre-AIA § 102(a)/(b) and AIA § 102(a)(1)/(2) — published/granted well before the August 16, 2016 priority date of US10346087.
• Brief description: Discloses a non-volatile memory device with a configurable ready/busy (R/B) output. The memory device can be configured (e.g., via a mode/configuration setting) to control how the R/B status is presented, including configurations that allow multiple memory devices to share a single R/B line — the device conditionally drives or releases its R/B output so that a controller can poll individual devices. This is squarely in the same technical field as US10346087 (per-chip ready/busy signaling, shared status pins, controller polling of individual devices).
• How it was confirmed: Google Patents search results for "Configurable ready/busy control" returned a page listing US10346087B2 among patents citing US8429313B2 — i.e., US8429313B2 is a backward citation (prior art) of US10346087B2.

2. US 2008/0205153 A1 — "Method and apparatus for controlling two or more non-volatile memory devices"

• Applicant: Samsung Electronics Co., Ltd.
• Publication date: August 28, 2008 (application published)
• Status relative to US10346087: Prior art under pre-AIA § 102(a)/(b) and AIA § 102(a)(1)/(2) — published before the August 16, 2016 priority date.
• Brief description: Discloses a method/apparatus for controlling two or more non-volatile memory devices, including handling of chip-enable signaling and status/ready-busy monitoring across multiple memory devices, in the same multi-device, controller-centric architecture addressed by US10346087.
• How it was confirmed: Appeared in the "Citations (4)" list on the Google Patents page of family member US20210294517A1 (the snippet: "US20080205153A1 (en) * 2007-02-23 | 2008-08-28 | Samsung Electronics Co., Ltd. | Method and apparatus for controlling two or more non-volatile memory devices"). Because US20210294517A1 is a continuation-family member of US10346087, this reference may have been cited during prosecution of the family. Caveat: I could not confirm that US20080205153A1 appears on the face of US10346087 itself as opposed to only in the continuation application's file history — treat this as a probable cited reference needing verification.

Claim-mapping analysis (potential § 102 anticipation)

Because the exact claim language is reconstructed, the analysis below maps each reference against the three independent claims as summarized from the Google Patents "Definitions" section.

Against Claim 1 (apparatus: two-state first signal → three-state second signal)

• US8429313B2 (Configurable ready/busy control): Potentially the strongest anticipatory reference. It addresses a memory device whose R/B output behavior is configurable, which is the same inventive field as US10346087's gating of the state output based on control signaling (chip enable / initially set function command). Whether it discloses the specific combination of (i) a state-signal generating circuit producing a two-state internal signal and (ii) an output control circuit producing a three-state output (0, 1, Hi-Z) gated by chip enable or a "CE reduction command" would determine anticipation. If US8429313B2 discloses tri-stating the R/B pin when the device is not selected, it could anticipate Claim 1 — this is the key question to resolve with the actual claim text and the full disclosure of US8429313B2.
• US20080205153A1: Relevant to the multi-device control context but less likely to disclose the specific tri-state (0/1/Hi-Z) output-control circuit of Claim 1; more likely relevant under § 103 for the system claims.

Against Claim 2 (system: wired-AND, three logic levels, chip enable / initially set function command)

• US8429313B2: Relevant — a configurable R/B scheme that permits multiple devices to share a single status line is conceptually the wired-AND + tri-state approach. Anticipation would hinge on whether it discloses the controller transmitting a chip-enable signal and/or an initially set function command, with each chip outputting one of three logic levels per its internal state.
• US20080205153A1: Relevant to the multi-device + chip-enable architecture of Claim 2; the disclosure of controlling two or more non-volatile memory devices with shared signaling is directly on point for the system context, though the "three logic levels" limitation would need to be found in the disclosure.

Against Claim 3 (system: output on enable, Hi-Z on disable)

• US8429313B2: This claim is the most functional/broadest (enable → drive status; disable → Hi-Z). A configurable R/B control that releases the R/B line when a device is not being polled/selected would map closely onto this claim. High anticipation risk if US8429313B2 discloses conditional driving/releasing of the R/B output.
• US20080205153A1: Also relevant to the enable/disable gating behavior across multiple devices.

References that are NOT prior art (excluded)

• US 2021/0294517 A1, US 11,003,382 B2, US 11,847,339 B2, US 12,189,976 B2 — these are continuation-family members of US10346087 (later filings, 2019–2023), not prior art. They cite US10346087, confirming the family, but they cannot anticipate it.
• The Apple design patent D593,087 and the Kikuchi Shinichi application 10,346,087 surfaced in earlier searches are unrelated, non-matching identifiers and were excluded per the literal-ID rule.

References described in the specification (not necessarily formal citations)

US10346087's own Background describes the prior-art landscape: (i) a system with a single wired-AND RnB pin shared by all ways (its FIG. 1/2) where the controller cannot identify which way is busy, and (ii) a system with per-way RnB pins (its FIG. 3) requiring excessive controller pads. These are prior-art systems discussed in the specification; they are not necessarily patent citations on the face of the patent, but they are the problem statement the invention addresses.

Bottom line

• Confirmed prior-art citations found: US 8,429,313 B2 ("Configurable ready/busy control") and US 2008/0205153 A1 ("Method and apparatus for controlling two or more non-volatile memory devices"), both Samsung, both well before the 2016 priority date.
• US8429313B2 is the most significant potential § 102 reference — its configurable ready/busy output that permits sharing a single status line across devices is the closest known art to the tri-state (0/1/Hi-Z) gated state-output of US10346087.
• Cannot fully complete the anticipation analysis without (1) the complete USPTO citation list for US10346087 (which I could not fully retrieve in the available steps) and (2) the verified, numbered claim text. I recommend pulling the official USPTO Patent Center record and the Google Patents "Citations" tab to close both gaps before any formal opinion is issued.

I have gathered what I can from the available searches (the tool budget is now exhausted). Below is my § 103 obviousness analysis for US 10,346,087, built from (a) the reconstructed independent claims, and (b) the prior-art references identified in the searches.

Obviousness Analysis — US 10,346,087 (35 U.S.C. § 103)

0. Preliminary caveat on claim scope

The full claim text of the issued patent was not retrievable in the searches; the three independent claims are reconstructed from the Google Patents "Definitions" extracts and the continuation family (e.g., US 2021/0294517 A1, which is part of the same family and shows the "wired-AND / state-check interval / CE reduction command" claim language). The analysis assumes the following claim elements:

• Claim 1 (apparatus): a state signal generating circuit generating a first signal indicative of an internal operation state (one of two states, e.g., ready/busy); a state signal output control circuit receiving the first signal and outputting a second signal (one of three states: logic 0, logic 1, Hi-Z) to an output pad based on at least one of a chip enable signal and an initially set function command (e.g., a "CE reduction command").
• Claim 2 (system — three logic levels): a plurality of memory chips each with a first state output pin; a controller with a first state input pin connected to the chips' pins in a wired-AND configuration; the controller transmits a chip enable signal and/or an initially set function command; each chip outputs a first state signal at one of three logic levels according to its internal operation state.
• Claim 3 (system — enable/disable): each chip, in response to an enable signal, outputs a first state signal based on its internal operation state; in response to a disable signal, outputs a high-impedance state.

1. Prior-art references identified (with key disclosures)

A. US 8,429,313 B2 — "Configurable ready/busy control" (SanDisk; Smith & Gorobets; filed May 27, 2004; granted Apr. 23, 2013)

URL: https://patents.google.com/patent/[US8429313B2](/patent/US8429313B2)/en

This is the single most damaging reference for the independent claims:

• Shared RnB pin to reduce pin count: "Both memory units 1 and 2 have ready/busy outputs that are connected to a common ready/busy pin … The ready/busy pin is shared to reduce the pin count of both packages and thus reduce the cost and complexity of the system." (FIGS. 1–2.)
• Selection-based gating of the status output (Claim 3 element): "A signal may automatically be sent from a selected memory unit and masked from an unselected unit." The AUTO/SELECT/DISABLE control register bits determine whether the output is driven (e.g., "Internal Busy 412," "Cache Busy 408," "Array Busy 406," "Other Busy 526") or forced to 0 when unselected (LINE 2, LINE 7 of the truth table: DieSelected=0, AUTO=1 → Output=0). This is functionally the enable/disable gating the patent claims, with the unselected output masked.
• Controller-configured status output (Claim 1 "initially set function command" element): "a busy control register that may be written by a controller. The contents of the busy control register determine whether a signal is sent from the memory unit to the controller and, if so, which of a plurality of signals is sent." This is a controller-set configuration command that selects which internal state is reflected on the pin — directly analogous to the "initially set function command" and to the selectable PASS/FAIL / die / plane state outputs of FIGS. 8A–8B and 10 of the patent.
• Multi-state internal status: internal busy, cache busy, array busy, other busy — multiple internal operation states selectable for output, analogous to the patent's first/second state pins.

B. US 8,433,845 B2 — "Data storage device which serializes memory device ready/busy signals" (Google Inc.; filed Apr. 8, 2009; granted Apr. 30, 2013)

URL: https://patents.google.com/patent/US20150363342 (cited in the family)

• Serializes the ready/busy signals of multiple memory devices so the controller can determine the per-device ready/busy state with a reduced number of status pins — addressing the identical problem (per-way state visibility vs. pin count) that US 10,346,087 addresses.

C. US 2017/0018296 A1 — "Semiconductor memory device outputting read-busy signal and memory system including the same" (SK Hynix; priority Jul. 13, 2015; published Jan. 19, 2017 — before the '087 priority date of Aug. 16, 2016)

• Cited on the face of the continuation family (US 2021/0294517 A1). Discloses a memory device that outputs a read-busy signal and a system using it — evidence that outputting operation-specific status (read-busy) on the status pin was known before the '087 priority date.

D. US 2008/0205153 A1 — "Method and apparatus for controlling two or more non-volatile memory devices" (Samsung; published Aug. 28, 2008)

• Also cited on the face of the family. Discloses a controller controlling two or more NVM devices — including per-device enable/control signaling of the type used in the '087's CE-based per-way status checking.

E. US 2016/0254038 A1 — "Nonvolatile memory devices, memory systems and related control methods" (Samsung; published Sep. 1, 2016)

URL: https://freepatentsonline.com/y2016/0254038.html

• Teaches using a set-feature command (a controller-issued, initially configured function command) to configure memory-device behavior (read mode tRC_En/tRC_Dis). This is direct evidence that "initially set function command" configuration of a NAND device's status/output behavior was routine and well known before the '087 priority date.

F. US 2002/0021598 A1 (Samsung; priority Aug. 8, 2000) and US 9,093,132 B2 / US 2016/0254038 (Samsung)

• Early Samsung work on interleaving multiple nonvolatile memories using chip-enable "don't care" intervals and ready/busy signaling; and per-plane ready/busy signaling (US 9,093,132) — showing that both chip-enable-based device selection and multi-state status signaling were already established in Samsung's own earlier art.

G. US 9,507,704 B2 — "Storage module and method for determining ready/busy status of a plurality of memory dies" (SanDisk; filed Jul. 31, 2014; granted Nov. 29, 2016)

• Same problem space: determining which of several memory dies sharing status pins is ready/busy.

2. Obviousness combinations and motivation

Combination 1 — Claims 1 and 3 (apparatus; enable/disable Hi-Z behavior)

Primary: US 8,429,313 B2 (SanDisk), as modified by standard tri-state/open-drain output practice (JEDEC NAND RnB) and/or US 8,433,845 B2.

Element mapping:

• State signal generating circuit / two-state first signal: US 8,429,313 discloses per-unit busy signals (internal busy, cache busy, array busy) — binary status signals.
• State signal output control circuit outputting three states (0, 1, Hi-Z) based on chip enable/selection: US 8,429,313's ready/busy control circuit (FIG. 5, ready/busy control circuit 646/650) gates the output on DieSelected/AUTO, masking unselected units. The only delta from claim 3 is that US 8,429,313's truth table shows a forced "0" output for unselected units (LINE 2: Output=0) rather than an explicit high-impedance state. Driving a shared open-drain/tri-state status line into high impedance when deselected was, however, utterly conventional in NAND design (open-drain wired-OR RnB per JEDEC; tri-state output buffers are textbook). A PHOSITA would have had a well-known, finite design choice: implement the "mask" as either a forced level or a Hi-Z. Replacing a forced-low mask with a Hi-Z mask on a shared line is an obvious design variant that preserves the exact same function (only the selected unit drives the line).

Motivation: SanDisk's own reference states the goal explicitly — reduce pin/line count by sharing one ready/busy line, while retaining the ability to know which unit is busy. The '087 patent's advance is not the concept (SanDisk's register-masked shared RnB is that concept) but the specific correlation of the shared RnB level with the per-way chip-enable timing so the controller can attribute the level to a specific way. That correlation is a straightforward implementation detail — the controller already generates per-chip CE signals and already samples RnB; combining the two signals in the controller is an obvious design step.

Combination 2 — Claim 2 (system; wired-AND; three logic levels)

Primary: US 8,429,313 B2, in view of US 8,433,845 B2 and US 2017/0018296 A1.

• Wired-AND first state input pin: US 8,429,313 FIG. 2 shows both memory units' ready/busy outputs tied to a common pin/line; wired-AND sharing of RnB was standard. US 8,433,845 explicitly serializes/shared ready-busy lines for multiple devices.
• Three logic levels on the shared pin: combining (i) SanDisk's selected-unit-drives/unselected-unit-masked output with (ii) the conventional tri-state/open-drain Hi-Z yields exactly the three levels (0, 1, Hi-Z). The "third" level is simply the conventional high-impedance state of a tri-state driver — no new circuitry, no unexpected result.
• Controller transmitting CE and/or function command and checking per-chip state: US 8,429,313's controller writes the busy-control register (function command) and uses die-selection; US 2008/0205153 A1 (Samsung, cited on the family) teaches per-device control of two or more NVM devices.

Motivation: The prior art collectively identifies the same problem the '087 patent solves: shared status pins lose per-device attribution, and per-device pins cost pads. SanDisk's solution (selection-masked status output) plus the conventional tri-state implementation plus CE-based sampling gives the full claim-2 system. The "CE reduction command" alternative is merely a controller-generated timing/configuration command (cf. US 2016/0254038's set-feature command), and US 8,429,313's register-write command already teaches controller-configured status-output behavior.

Combination 3 — "Initially set function command" limitations (Claims 1–2)

US 8,429,313 B2 (busy control register written by controller) + US 2016/0254038 A1 (set-feature command configuring device behavior).

The "initially set function command (CE reduction command)" is squarely a set-feature-type command: a controller writes a register/setting that defines how the device behaves thereafter (here: the CE timing/window during which the status pin is driven). US 8,429,313's busy-control register is exactly such a controller-written setting controlling status-pin behavior; US 2016/0254038 shows Samsung itself using set-feature commands to configure read-mode/status behavior. Combining a known configuration command mechanism with a known selection-masked status output is an obvious aggregation — each element performs its known function, no synergy.

3. Reasons a PHOSITA would have been motivated to combine

1. Pin/pad-cost reduction: Every reference in this art (SanDisk '313, Google '845, SanDisk '704) states the same motivation — reduce controller/packaging pin count by sharing ready/busy lines. The '087 patent pursues the same goal.
2. Per-device state visibility: SanDisk '313 identifies the core deficiency of a shared RnB ("it is not known which memory unit is busy") and proposes selection-masked output as the fix; the '087 patent is a specific implementation of that same fix using CE timing correlation. There is a documented design trajectory from '313 → '845 → '704 → '087.
3. Conventional building blocks: Tri-state output buffers, open-drain wired-AND RnB, chip-enable-based device selection, and set-feature commands were all standard, well-documented NAND design elements by 2016. Combining them requires no inventive skill — only routine engineering.
4. Same field, same problem: All references are in the NAND/flash memory-controller interface art (G11C7/10, G11C7/1063, G11C16/00 — the '087's own classifications), so a PHOSITA would consult them and apply them to the shared-RnB multi-way problem.
5. The specification itself concedes the problem is known: The '087 background describes the wired-AND single-RnB system (FIG. 1) and the per-way pin system (FIG. 3) as prior art, and the state-read-command alternative (FIG. 4) as prior art. The claimed solution — gating the RnB output by CE to create a tri-state shared line — is a predictable combination of those known elements.

4. Secondary considerations

From the searches: no evidence of long-felt need, industry praise, licensing, copying, or unexpected results attributable to the '087 claims. The patent has not been asserted in litigation (per the earlier litigation summary), and its family continuations (US 11,003,382; US 11,847,339; US 12,189,976) suggest routine portfolio prosecution rather than a pioneering advance. The absence of objective indicia of non-obviousness strengthens a § 103 case.

5. Strongest rejection framework

The AIA effective prior-art dates all precede the '087 priority date (Aug. 16, 2016): US 8,429,313 (filed 2004), US 8,433,845 (filed 2009), US 2016/0254038 (published Sep. 1, 2016 — just after the priority date, so use the Korean priority/filing if needed, or drop it and rely on '313's register-command teaching), US 2017/0018296 (priority Jul. 13, 2015), US 2008/0205153 (published 2008).

6. Honest limitations of this analysis

• Claim text is reconstructed, not verified against the issued PDF. A formal rejection requires the exact claim language, particularly the recitation of the "initially set function command" and whether Claim 1 requires both CE and the function command (the spec describes "at least one of … or both").
• US 2016/0254038 A1 published days after the Aug. 16, 2016 priority date; if it is used, the earlier-filed application (Samsung's 2015/2016 filings) must be checked for § 102(e) availability, or it should be used only as evidence of the state of the art.
• US 8,429,313 B2 does not literally disclose "high impedance" on deselect (its truth table shows forced-low masking); the Hi-Z element rests on the obviousness of tri-state implementation, which is strong but should be argued explicitly with a textbook/JEDEC citation if available.
• The examiner's own cited art on the family (US 2007/0005825 A1, US 2008/0205153 A1, US 2017/0018296 A1) is the best starting point for a formal § 103 ground; US 8,429,313 B2 was not identified as an examiner citation in the searches and may not have been before the examiner — making it a potentially powerful new reference.

Bottom line: A strong prima facie § 103 case can be built around US 8,429,313 B2 as the primary reference for all three independent claims, with the tri-state/Hi-Z and wired-AND elements supplied by conventional NAND design practice and US 8,433,845 B2 / US 2017/0018296 A1. The claimed combination is a predictable, conventional implementation of a known problem-solution (shared status pin with selection-gated output), and no objective indicia of non-obviousness were found.