Derivative works

Defensive Disclosure: Derivative Works for US Patent 9905691B2

Patent Title: Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
Patent Number: US9905691B2
Current Assignee: Oak Ip LLC
Expiration Date: October 10, 2023 (Expired - Fee Related)
Current Date: April 26, 2026

This document outlines several derivative variations of the technology described in US Patent 9905691B2, intended to serve as defensive prior art. These disclosures aim to render potential incremental improvements or alternative implementations of the core inventive concept—depinning the Fermi level of a semiconductor at an electrical junction using a thin interface layer—as obvious or non-novel, thereby limiting the scope for future patenting by competitors. The focus is on technical feasibility and specific implementation details across various domains and operational parameters.

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Derivatives for Independent Claim 1

Claim 1: An electrical device comprising: a conductor; a silicon-based semiconductor having a surface; and an interface layer disposed between and in contact with the conductor and the silicon-based semiconductor, the interface layer configured to depin the Fermi level of the silicon-based semiconductor at an interface with the conductor and to permit electrical current to flow between the conductor and the silicon-based semiconductor when the electrical device is biased, wherein the specific contact resistance of the electrical device is less than approximately 10 Ω-μm², the interface layer comprising a passivation layer and a separation layer, and the interface layer being sufficiently thin to permit direct tunneling of electrons between the conductor and the silicon-based semiconductor.

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1. Material & Component Substitution Derivatives

Derivative 1.1: Wide Bandgap Semiconductor with Boron Nitride Interface

• Enabling Description: This derivative features a conductor (e.g., TiN alloy) interfacing with a wide bandgap silicon carbide (SiC) semiconductor substrate (4H-SiC, n-type doped to 10^17 cm^-3). The interface layer is composed of a monolayer passivation layer of hexagonal boron nitride (hBN) directly grown on the SiC surface via chemical vapor deposition (CVD) using borane and ammonia precursors at 1000°C. A subsequent separation layer of ultra-thin aluminum nitride (AlN, 2-3 monolayers) is deposited via atomic layer deposition (ALD) using trimethylaluminum (TMA) and ammonia, specifically engineered for a bandgap offset to minimize MIGS penetration into the SiC. The hBN provides robust surface passivation by saturating dangling bonds on the SiC, while the AlN acts as a tunable tunnel barrier and spatial separator. The TiN conductor is then sputtered onto the AlN, achieving a specific contact resistance below 1 Ω-μm² through direct tunneling, with the Fermi level of the SiC depinned due to the hBN/AlN stack. The TiN work function is tuned to align with the SiC conduction band.

graph TD
    A[Conductor: TiN Alloy] --> B{Interface Layer};
    B --> C[Separation Layer: Ultra-thin AlN];
    C --> D[Passivation Layer: hBN Monolayer];
    D --> E[Semiconductor: 4H-SiC (n-type)];
    E -- Depinning --> F(Depinned Fermi Level);
    F -- Current Flow --> G(Low Specific Contact Resistance < 1 Ω-μm²);
    G -- Direct Tunneling --> A;

Derivative 1.2: Germanium-Tin Semiconductor with High-k Oxide/Polymer Hybrid Interface

• Enabling Description: This derivative utilizes a strained Germanium-Tin (GeSn) alloy (n-type, 10% Sn concentration) as the semiconductor. The interface layer consists of a primary passivation layer of hafnium oxynitride (HfON) approximately 0.5 nm thick, formed by plasma nitridation of an ALD-grown HfO2 film on the GeSn. A novel separation layer comprising a few monolayers (approx. 1-2 nm) of a functionalized poly(methyl methacrylate) (PMMA) derivative, specifically engineered with high electron affinity and low defect density, is then spin-coated and cured. The PMMA acts as a dielectric spacer, and its chemical functionalization enhances adhesion and minimizes interface states. A low-work-function metal (e.g., Ytterbium-doped Aluminum alloy) is deposited via electron-beam evaporation. The HfON passivates the GeSn surface, while the PMMA separation layer effectively displaces the metal-induced gap states, ensuring Fermi level depinning and enabling tunneling with specific contact resistance below 5 Ω-μm².

graph TD
    A[Conductor: Yb-Al Alloy] --> B{Interface Layer};
    B --> C[Separation Layer: Functionalized PMMA (1-2nm)];
    C --> D[Passivation Layer: HfON (0.5nm)];
    D --> E[Semiconductor: Strained GeSn (n-type)];
    E -- Depinning --> F(Depinned Fermi Level);
    F -- Current Flow --> G(Low Specific Contact Resistance < 5 Ω-μm²);
    G -- Direct Tunneling --> A;

Derivative 1.3: Metallic Glass Conductor with Graphene Oxide Interface

• Enabling Description: This derivative employs a bulk metallic glass (BMG) conductor, such as Zr-Cu-Ni-Al alloy, known for its amorphous structure and tunable work function. The semiconductor is a p-type silicon-germanium (SiGe) alloy (20% Ge concentration). The interface layer is a precisely controlled few-layer graphene oxide (GO) film (1-2 nm thickness), prepared by spin-coating an exfoliated GO solution and then partially reducing it using pulsed laser annealing to create specific passivation sites (e.g., hydroxyl and epoxy groups) on the SiGe surface while maintaining sufficient dielectric properties for separation. The partial reduction also tunes the electronic properties of the GO for optimal band alignment. The BMG conductor is deposited via magnetron sputtering onto the GO layer. This configuration effectively passivates the SiGe surface and spatially separates it from the BMG, leading to Fermi level depinning and allowing hole tunneling with a specific contact resistance less than 10 Ω-μm².

graph TD
    A[Conductor: Bulk Metallic Glass (Zr-Cu-Ni-Al)] --> B{Interface Layer};
    B --> C[Passivation/Separation Layer: Partially Reduced Graphene Oxide (1-2nm)];
    C --> D[Semiconductor: p-type SiGe (20% Ge)];
    D -- Depinning --> F(Depinned Fermi Level);
    F -- Current Flow --> G(Low Specific Contact Resistance < 10 Ω-μm²);
    G -- Direct Tunneling (Holes) --> A;

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2. Operational Parameter Expansion Derivatives

Derivative 1.4: Cryogenic Operation for Quantum Computing Interfaces

• Enabling Description: This device is optimized for operation at cryogenic temperatures (e.g., 4 Kelvin for superconducting quantum computers). The semiconductor is a lightly doped silicon-on-insulator (SOI) substrate. The conductor is a superconducting aluminum (Al) film. The interface layer consists of an ultra-thin (0.3 nm) silicon nitride passivation layer formed by low-temperature plasma nitridation, followed by a 1 nm thick amorphous silicon oxide (a-SiO2) separation layer grown by low-temperature ALD. The materials are selected for minimal thermal expansion mismatch and stable dielectric properties at cryogenic temperatures. The depinning of the Fermi level and the low specific contact resistance (< 10 Ω-μm²) are maintained at 4K, enabling highly efficient, non-ohmic contacts for sensitive quantum devices where precise band alignment and minimized charge traps are critical. The direct tunneling mechanism is preserved in the superconducting state of the aluminum.

stateDiagram-v2
    [*] --> Off
    Off --> Cooling: Initiate
    Cooling --> Cryogenic_Ready: Temp < 10K
    Cryogenic_Ready --> Operating_Mode: Apply Bias
    Operating_Mode --> Depinning_Active: Fermi Level Tuned
    Depinning_Active --> Current_Flow: Direct Tunneling
    Current_Flow --> Operating_Mode: Continuous Operation
    Operating_Mode --> Cooling: Shutdown
    Cooling --> Off

Derivative 1.5: High-Frequency (THz) Rectifier with Optimized Layer Thickness

• Enabling Description: This derivative is a high-frequency (terahertz, THz) rectifier designed for minimal parasitic capacitance and inductance, achieving efficient signal conversion. The silicon-based semiconductor is a heavily n-doped silicon (n+-Si) substrate. The conductor is a plasmonic gold (Au) nanostructure, tailored for THz resonance. The interface layer comprises an ultra-thin (0.1 nm) silicon hydride (SiH) passivation, formed by hydrogen plasma treatment, followed by a sub-nanometer (0.5 nm) layer of calcium fluoride (CaF2) as a separation layer, deposited by molecular beam epitaxy (MBE). The precise, atomically thin interface layer is crucial for maintaining direct tunneling at THz frequencies and minimizing carrier transit time. The depinned Fermi level allows for an optimized Schottky barrier height for THz rectification, maintaining specific contact resistance below 1 Ω-μm² under high-frequency AC bias conditions.

flowchart TD
    A[THz Signal Input] --> B(Plasmonic Au Conductor)
    B --> C{Interface Layer};
    C --> D[Separation Layer: CaF2 (0.5nm)];
    D --> E[Passivation Layer: SiH (0.1nm)];
    E --> F[Heavily n-doped Si Semiconductor];
    F -- Rectified Current --> G[THz Output];
    C -- Minimize Parasitics --> B;
    C -- Direct Tunneling @ THz --> F;

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3. Cross-Domain Application Derivatives

Derivative 1.6: Bio-Integrated Neuro-Prosthetic Interface

• Enabling Description: This device targets bio-integration, specifically as an interface for neuro-prosthetics, requiring biocompatibility and stable electrical contact with neural tissue. The "conductor" is a flexible, biocompatible conductive polymer electrode (e.g., PEDOT:PSS with embedded gold nanoparticles). The "silicon-based semiconductor" is a silicon neural probe, where the surface interacting with tissue requires stable electrical properties. The interface layer consists of a silicon oxynitride (SiON) passivation layer (0.5 nm thick), formed by plasma-enhanced CVD (PECVD), providing biocompatibility and chemical stability. A subsequent 1-2 nm separation layer of albumin protein (a naturally occurring biocompatible molecule) is covalently bonded to the SiON surface, isolating the conductive polymer from the silicon. The depinned Fermi level at the SiON/albumin interface allows for stable, low-noise signal transduction with neural tissue, mimicking ohmic-like behavior for both ion-electron conversion and signal transmission, maintaining effective specific contact resistance below 10 Ω-μm².

classDiagram
    class NeuralProbe {
        +SiliconSubstrate
        +InterfaceLayer
        +BiocompatibleElectrode
    }
    class InterfaceLayer {
        +SiONPassivationLayer
        +AlbuminSeparationLayer
    }
    class BiocompatibleElectrode {
        +ConductivePolymer
        +GoldNanoparticles
    }
    NeuralProbe "1" -- "1" InterfaceLayer : contains
    InterfaceLayer "1" -- "1" BiocompatibleElectrode : interfaces_with
    NeuralProbe -- "1" NeuralTissue : contacts
    NeuralTissue : +SignalTransduction()

Derivative 1.7: Agricultural Soil Moisture and Nutrient Sensor

• Enabling Description: This device functions as a durable, long-life sensor for in-situ soil moisture and nutrient levels in agricultural applications. The "silicon-based semiconductor" is a porous silicon (p-Si) structure, providing a large surface area for sensing. The "conductor" is a robust, corrosion-resistant iridium (Ir) electrode. The interface layer on the p-Si is a silicon hydride/fluoride (SiHx/SiFy) monolayer passivation, formed by etching in HF solution and subsequent hydrogen anneal, providing chemical stability against soil acidity/alkalinity. A novel separation layer of a few nanometers of a humidity-sensitive conductive polymer (e.g., polyaniline) is then deposited via electropolymerization. The depinning of the Fermi level at the p-Si/interface layer junction ensures stable baseline electrical characteristics. Variations in soil moisture or nutrient ion concentration alter the dielectric properties or doping of the polymer layer, inducing a measurable change in the junction's specific contact resistance (below 10 Ω-μm² under baseline conditions) due to modified tunneling, which is then correlated to environmental parameters.

erDiagram
    Agricultural_Sensor ||--o{ Soil_Environment : interacts_with
    Agricultural_Sensor {
        UUID SensorID
        double BaselineResistance
        string CalibrationData
    }
    Soil_Environment {
        double MoistureLevel
        double NutrientConcentration
        double Temperature
        double pH
    }
    Agricultural_Sensor ||--|{ Sensing_Element : comprises
    Sensing_Element {
        string ElementType
    }
    Sensing_Element ||--|{ P_Si_Semiconductor : uses
    P_Si_Semiconductor ||--|{ Interface_Layer : has
    Interface_Layer ||--|{ Ir_Conductor : connects_to
    Interface_Layer {
        string PassivationMaterial (SiHx/SiFy)
        string SeparationMaterial (Polyaniline)
        double TunnelingResistance
    }

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4. Integration with Emerging Tech Derivatives

Derivative 1.8: AI-Optimized Interface for Neuromorphic Computing

• Enabling Description: This variant is an AI-optimized "synaptic" junction for neuromorphic computing. The silicon-based semiconductor is a lightly doped silicon substrate designed as a memristor channel. The conductor is a platinum (Pt) electrode. The interface layer is a dynamically tunable titanium oxynitride (TiON) film (0.8-1.5 nm thick), formed by reactive sputtering with real-time plasma parameter adjustment (N2/O2 ratio, power, pressure). An AI model, trained on in-situ impedance spectroscopy and X-ray photoelectron spectroscopy (XPS) data during deposition, continuously adjusts sputtering parameters to precisely control the TiON stoichiometry and defect density. This AI control ensures optimal Fermi level depinning and a specific contact resistance below 10 Ω-μm² for varying "synaptic weights." The AI can programmatically adjust the TiON thickness and composition to emulate different synaptic strengths by altering the tunneling probability and barrier height, enabling adaptive learning within the neuromorphic network.

sequenceDiagram
    participant AI as AI_Controller
    participant SPU as Sputtering_Process_Unit
    participant ISS as InSitu_Spectroscopy_Sensors
    participant NPU as Neuromorphic_Processing_Unit

    AI->SPU: Set_Sputtering_Parameters(Initial)
    SPU->ISS: Deposit_TiON_Layer()
    ISS->AI: Feedback_Data(Impedance, XPS)
    loop Optimization Cycle
        AI->AI: Analyze_Feedback_Data()
        AI->AI: Predict_Interface_Properties()
        AI->SPU: Adjust_Sputtering_Parameters(Optimized)
        SPU->ISS: Continue_Deposition()
        ISS->AI: Feedback_Data()
    end
    AI->NPU: Configure_Junction_Weights(Final_Properties)
    NPU->NPU: Perform_Neuromorphic_Operation()

Derivative 1.9: IoT-Monitored Self-Correcting Power Diode

• Enabling Description: This high-power rectifier incorporates IoT sensors for real-time monitoring and self-correction. The semiconductor is a vertically integrated silicon power diode. The conductor is a heavily doped polysilicon contact. The interface layer is a silicon nitride (SiN) layer (1-2 nm), precisely grown via remote plasma nitridation. Integrated micro-sensors (e.g., thermistors, voltage probes) within the polysilicon conductor and near the SiN interface constantly stream operational data (temperature, forward voltage drop, leakage current) via a low-power IoT module. An edge computing unit analyzes this data to detect deviations from optimal specific contact resistance (initially below 10 Ω-μm²). If degradation is detected (e.g., due to hot carrier injection or thermal stress causing trap formation), the system can activate a localized, sub-threshold current pulse or a mild annealing sequence to "self-correct" by re-passivating localized defects or re-aligning atomic structures within the interface layer, thereby restoring Fermi level depinning and maintaining efficient current flow.

graph LR
    A[Silicon Power Diode] -- Interface Layer (SiN) --> B[Polysilicon Conductor]
    B -- Embed --> C[Micro-Sensors (Temp, Voltage, Leakage)]
    C -- Data Stream --> D[IoT Module]
    D -- Wireless Link --> E[Edge Computing Unit]
    E -- Analyze Data --> F{Anomaly Detection};
    F -- Degradation Detected --> G[Self-Correction Module];
    G -- Localized Pulse/Anneal --> A;
    F -- No Anomaly --> E;

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5. The "Inverse" or Failure Mode Derivatives

Derivative 1.10: Security-Enhanced Disposable Junction with Programmable Degradation

• Enabling Description: This derivative describes a "disposable" or single-use electrical junction for sensitive data handling or anti-tamper applications, designed for controlled degradation. The silicon-based semiconductor is a secure memory element. The conductor is a tungsten (W) contact. The interface layer consists of a silicon oxide (SiO2) passivation layer (0.5 nm) formed by rapid thermal oxidation, followed by a 1 nm separation layer made of a photo-degradable polymer (e.g., a spiropyran-containing copolymer) doped with a small concentration of conductive nanoparticles (e.g., carbon nanotubes). Upon exposure to a specific wavelength of UV light (the "kill switch") or a predetermined thermal excursion, the polymer rapidly cross-links or fragments, significantly increasing its resistivity and altering its band structure. This intentionally disrupts the Fermi level depinning, increasing the specific contact resistance beyond 100 Ω-μm² (effectively "opening" the circuit) and making the memory element unreadable, thus providing a secure, programmable failure mechanism.

stateDiagram-v2
    state "Normal Operation" as Normal
    state "Degradation Triggered" as Triggered
    state "High Resistance State" as Degraded

    [*] --> Normal
    Normal --> Triggered: UV Exposure OR Thermal Excursion
    Triggered --> Degraded: Polymer Degradation / Reconfiguration
    Degraded --> Degraded: (Irreversible)
    Normal --> Normal: Continuous Current Flow
    Degraded --> HighResistance: No Current Flow / High Resistance

Derivative 1.11: Self-Healing Junction for Aerospace Applications

• Enabling Description: This robust electrical junction is designed for self-healing capabilities in harsh aerospace environments where minor defects could compromise system integrity. The semiconductor is radiation-hardened silicon-on-sapphire (SOS). The conductor is a high-reliability platinum-iridium (PtIr) alloy. The interface layer initially consists of a nitrogen-doped silicon oxide (SiOxNy) passivation layer (1 nm thick), providing excellent radiation resistance. Embedded within this SiOxNy separation layer are microencapsulated polymer-based healing agents (e.g., dicyclopentadiene monomer with Grubb's catalyst), designed to rupture upon micro-crack formation or localized electrical breakdown. When a defect occurs, the healing agent polymerizes, physically repairing the dielectric gap and chemically interacting with newly exposed dangling bonds on the SiOxNy surface. This process restores the spatial separation and passivation, re-establishing Fermi level depinning and maintaining specific contact resistance below 10 Ω-μm², ensuring continued functionality after minor damage events.

graph TD
    A[PtIr Conductor] --> B{Interface Layer};
    B --> C[SiOxNy with Healing Agent Microspheres];
    C --> D[Radiation-Hardened SOS Semiconductor];
    D -- Optimal Contact --> E(Depinned Fermi Level, Low Resistance);

    subgraph Defect Event
        F(Micro-crack / Electrical Breakdown) --> G(Microsphere Rupture);
        G --> H(Healing Agent Release & Polymerization);
        H --> I(Defect Repair / Re-passivation);
        I --> E;
    end

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Combination Prior Art Scenarios

These scenarios combine the teachings of US9905691B2 with existing open-source standards, demonstrating how the patented concepts, or their natural extensions, could be anticipated or rendered obvious.

1. US9905691B2 + Open-Source Standard for Fin Field-Effect Transistors (FinFETs) (e.g., IEEE P2000 Series)

• Description: The core concept of depinning the Fermi level and achieving low contact resistance through an interface layer (as described in US9905691B2, specifically Claim 1) is applied to the source and drain contacts of a FinFET device, a widely adopted architecture in the semiconductor industry. Modern FinFET fabrication processes, detailed in open-source literature and standards (e.g., through universities, industry consortia like SEMI, or specific IEEE standards for device design and characterization), already address challenges of scaling and contact resistance. Combining the explicit teaching of US9905691B2 (a thin passivation and separation layer for depinning) with the well-known FinFET architecture and its need for improved source/drain contacts would be obvious to a person skilled in the art. The interface layer would be adapted to conform to the 3D fin geometry, for instance, by using conformal ALD techniques for nitride or oxide passivation as already commonly employed in FinFET manufacturing. This would enable low-resistance, depinned contacts critical for performance gains in advanced FinFET nodes.

2. US9905691B2 + Open-Source Standards for Flexible Hybrid Electronics (e.g., IPC-2221B for Printed Boards)

• Description: The methodology for forming depinned electrical junctions (as per US9905691B2, particularly Claim 11, involving heating in the presence of nitrogenous material) is integrated into flexible hybrid electronics (FHE) platforms. Open-source standards and research in FHE, such as material specifications and fabrication guidelines (e.g., sections of IPC-2221B or academic publications on flexible substrates), detail the use of various flexible polymer substrates (e.g., polyimide, PEN) and low-temperature processing. Applying the nitridation process for interface layer formation from US9905691B2 (with careful temperature control compatible with flexible substrates) to contacts on flexible silicon-based semiconductors (e.g., thin-film silicon on polymer) for FHE would be a straightforward adaptation. The depinned Fermi level junctions would enable highly efficient, low-resistance contacts for flexible sensors, displays, and wearable electronics, addressing known challenges in material compatibility and interface stability in FHE.

3. US9905691B2 + Open-Source Data Formats for Process Control in Semiconductor Manufacturing (e.g., SEMI E95 for Process Module Interface)

• Description: The detailed processes for forming interface layers, such as those described in US9905691B2 (e.g., Claim 12, heating in a vacuum chamber and exposing to nitrogenous material for precise thickness control), are combined with open-source data formats and communication protocols commonly used in semiconductor manufacturing equipment (e.g., SEMI E95 for equipment communication interfaces, or SECS/GEM standards). The explicit control over temperature, vacuum, and gas exposure duration for forming ultra-thin interface layers can be directly implemented and optimized using standard process control software and hardware interfaces. Integrating the parameters for nitrogenous material exposure and vacuum conditions into an automated recipe defined by SEMI standards would be an obvious engineering task for a fabrication facility. This enables reproducible manufacturing of junctions with depinned Fermi levels and minimum specific contact resistance, leveraging established, standardized process control frameworks.