Prior art

The provided "Full patent text" for US patent 9905691, sourced from Google Patents, does not contain a "References Cited" section that lists third-party prior art patents. Therefore, I cannot identify specific external patent references that act as prior art for anticipation under 35 U.S.C. § 102 based solely on the provided authoritative text.

However, the patent text includes a "RELATED APPLICATIONS" section, which lists several U.S. patents and patent applications to which US9905691 claims benefit as part of a continuing family. While these are "patent citations" within the document, they are generally not considered prior art for anticipation under 35 U.S.C. § 102 against US9905691 itself, as they share a common inventorship and priority date (2002-08-12 for the earliest application in the chain). Therefore, their content would typically be considered part of the same inventive disclosure.

Below are the patent citations listed in the "RELATED APPLICATIONS" section:

1. Full Citation: U.S. Pat. No. 8,431,469

   • Publication/Filing Date: Issued Apr. 30, 2013 (based on application Ser. No. 13/022,522, filed Feb. 7, 2011).
   • Brief Description: This patent is a family member (continuation/divisional) of the same inventive concept as US9905691. The content would be related to methods for depinning the Fermi level of a semiconductor and devices incorporating such junctions.
   • Potential Anticipation under 35 U.S.C. § 102: Not applicable as prior art. Due to shared priority (dating back to August 12, 2002), this patent generally cannot anticipate the claims of US9905691.

2. Full Citation: U.S. Pat. No. 7,884,003

   • Publication/Filing Date: Issued Feb. 8, 2011 (based on application Ser. No. 12/197,996, filed Aug. 25, 2008).
   • Brief Description: This patent is a family member (continuation/divisional) of the same inventive concept as US9905691, concerning methods and devices for depinning the Fermi level of a semiconductor at an electrical junction.
   • Potential Anticipation under 35 U.S.C. § 102: Not applicable as prior art. Due to shared priority (dating back to August 12, 2002), this patent generally cannot anticipate the claims of US9905691.

3. Full Citation: U.S. Pat. No. 7,462,860

   • Publication/Filing Date: Issued Dec. 9, 2008 (based on application Ser. No. 11/181,217, filed Jul. 13, 2005).
   • Brief Description: This patent is a family member (continuation/divisional) of the same inventive concept as US9905691, disclosing methods for depinning the Fermi level of a semiconductor at an electrical junction and related devices.
   • Potential Anticipation under 35 U.S.C. § 102: Not applicable as prior art. Due to shared priority (dating back to August 12, 2002), this patent generally cannot anticipate the claims of US9905691.

4. Full Citation: U.S. Pat. No. 7,084,423

   • Publication/Filing Date: Issued Aug. 1, 2006 (based on application Ser. No. 10/217,758, filed Aug. 12, 2002).
   • Brief Description: This is the earliest patent in the family explicitly mentioned, also covering methods for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions.
   • Potential Anticipation under 35 U.S.C. § 102: Not applicable as prior art. As the parent application, it provides the priority date for US9905691 and thus cannot anticipate its own claims.

5. Full Citation: U.S. Pat. No. 6,833,556

   • Publication/Filing Date: Issued Dec. 21, 2004, filed Jan. 14, 2003 (as U.S. patent application Ser. No. 10/342,576).
   • Brief Description: This patent, titled "Insulated Gate Field Effect Transistor Having Passivated Schottky Barriers to the Channel," is also explicitly related and incorporated by reference in US9905691. It describes an interface layer used in connection with a semiconductor surface of a channel in a field effect transistor.
   • Potential Anticipation under 35 U.S.C. § 102: Not applicable as prior art. While filed later than the priority date of the original application for US9905691 (Aug. 12, 2002), it is identified as a "related" application by the same inventors and assignee, and its content is incorporated by reference, suggesting it is part of the same overall inventive effort and not prior art under 35 U.S.C. § 102.

Non-Patent Literature References (explicitly discussed in the patent's background)

Although the request specifically asked for patent citations, it's important to note that the patent's background section explicitly discusses the following non-patent literature references, which are indeed prior art relevant to the invention:

• J. Tersoff, “Schottky Barrier Heights and the Continuum of Gap States,” Phys. Rev. Lett. 52 (6), Feb. 6, 1984. This reference is described as proposing a model to explain Fermi level pinning at a semiconductor-metal interface due to metal induced gap states (MIGS).
• Louie, Chelikowsky, and Cohen, “Ionicity and the theory of Schottky barriers,” Phys. Rev. B 15, 2154 (1977). This work is mentioned as foundational to Tersoff's model.

These non-patent literature references establish the scientific background and existing problems (Fermi level pinning, MIGS) that US9905691 aims to overcome.