Patent 9318609

Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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To identify the most relevant prior art for US patent 9318609, I will examine the "Citations" section of the patent itself, which lists prior art references cited by the examiner and/or third parties. This section is typically the most direct source of prior art considered during the patent's examination. I will then provide the requested information for each.

Here are the patent citations listed for US patent 9318609, along with their details:

Most Relevant Prior Art for US Patent 9318609

Below are the patent citations listed in US9318609B2, which represent prior art considered during its examination.

  1. US6043138A

    • Full Citation: US6043138A - Multi-step polysilicon deposition process for boron penetration inhibition
    • Publication Date: 2000-03-28 (Priority Date: 1996-09-16)
    • Brief Description: This patent describes a multi-step polysilicon deposition process to inhibit boron penetration in semiconductor devices. While not directly detailing fin structures or recessed isolation, it pertains to fabrication processes and material properties in transistors.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): Less likely to directly anticipate the structural claims of US9318609B2 (Claims 1, 5, 10) due to its focus on polysilicon deposition and impurity inhibition rather than the specific fin, isolation, and epitaxial layer geometry. It might be relevant to manufacturing aspects if those claims were broader, but given the specific structural elements claimed in US9318609B2, direct anticipation is unlikely. It could potentially serve as background art for general semiconductor fabrication.

  2. US6492216B1

    • Full Citation: US6492216B1 - Method of forming a transistor with a strained channel
    • Publication Date: 2002-12-10 (Priority Date: 2002-02-07)
    • Brief Description: This patent describes a method for forming a transistor with a strained channel, which is relevant to the objective of US9318609B2 to increase carrier mobility through crystal strain technology using epitaxial layers.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent is highly relevant as US9318609B2 explicitly mentions using strained silicon layers and epitaxial SiGe or SiC to improve device performance and carrier mobility, which is the core concept of US6492216B1. Claims 1, 5, 8, and 10 of US9318609B2, which describe the epitaxial layer and its function, could potentially be anticipated, especially regarding the broad concept of a strained channel formed by an epitaxial layer.

  3. US20040195624A1

    • Full Citation: US20040195624A1 - Strained silicon fin field effect transistor
    • Publication Date: 2004-10-07 (Priority Date: 2003-04-04)
    • Brief Description: This publication describes a strained silicon fin field effect transistor (FinFET). This is highly relevant as US9318609B2 also describes a semiconductor device with a fin structure and an epitaxial structure designed to impart stress.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This publication is extremely relevant, as it directly addresses "strained silicon fin field effect transistors." Claims 1, 5, 8, 9, and 10 of US9318609B2, which cover the fin structure, gate structure, isolation, epitaxial layer, and spacers, are highly susceptible to anticipation by this reference, particularly regarding the combination of finFET architecture with strained materials.

  4. US20050051825A1

    • Full Citation: US20050051825A1 - Semiconductor device and manufacturing method thereof
    • Publication Date: 2005-03-10 (Priority Date: 2003-09-09)
    • Brief Description: This publication describes a semiconductor device and its manufacturing method, likely involving structures relevant to FinFETs or strained channels.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): Without a more specific description of the device in US20050051825A1, it's difficult to pinpoint exact claim anticipation. However, given its publication date and general topic, it could potentially anticipate broader aspects of claims 1 and 5 relating to semiconductor device structures and manufacturing if it discloses similar fin, isolation, or epitaxial layer configurations.

  5. US6921963B2

    • Full Citation: US6921963B2 - Narrow fin FinFET
    • Publication Date: 2005-07-26 (Priority Date: 2003-01-23)
    • Brief Description: This patent specifically describes a "narrow fin FinFET," directly addressing the fin structure aspect of US9318609B2.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent is very relevant to Claim 1 of US9318609B2, which defines a semiconductor device with a fin structure. Depending on the specifics of the isolation structure and epitaxial layer in US6921963B2, it could anticipate elements of claims 1, 9, and 10.

  6. US20060099830A1

    • Full Citation: US20060099830A1 - Plasma implantation using halogenated dopant species to limit deposition of surface layers
    • Publication Date: 2006-05-11 (Priority Date: 2004-11-05)
    • Brief Description: This publication focuses on plasma implantation techniques using specific dopant species to limit surface layer deposition. This is a manufacturing process detail.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent is more focused on a specific fabrication technique (plasma implantation) rather than the overall device structure. It is unlikely to directly anticipate the structural claims of US9318609B2 (Claims 1, 5, 10). It could potentially be considered for method claims if US9318609B2 had any.

  7. US7087477B2

    • Full Citation: US7087477B2 - FinFET SRAM cell using low mobility plane for cell stability and method for forming
    • Publication Date: 2006-08-08 (Priority Date: 2001-12-04)
    • Brief Description: This patent describes a FinFET SRAM cell and a method for forming it, utilizing a low mobility plane for cell stability. It involves FinFET architecture.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent's discussion of FinFET SRAM cells and their formation is highly relevant to the FinFET aspects of US9318609B2. Claims 1, 9, and 10, which define the FinFET structure, could potentially be anticipated by this reference.

  8. US7091551B1

    • Full Citation: US7091551B1 - Four-bit FinFET NVRAM memory device
    • Publication Date: 2006-08-15 (Priority Date: 2005-04-13)
    • Brief Description: This patent describes a four-bit FinFET NVRAM memory device. It further demonstrates the existence of FinFET technology prior to US9318609B2.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): Similar to US7087477B2, this patent provides further evidence of FinFET technology. Claims 1, 9, and 10 of US9318609B2, relating to the FinFET structure, could be anticipated.

  9. US20060286729A1

    • Full Citation: US20060286729A1 - Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate
    • Publication Date: 2006-12-21 (Priority Date: 2005-06-21)
    • Brief Description: This publication discusses a CMOS integrated circuit utilizing raised source/drain regions and a replacement metal gate process. US9318609B2 also mentions a replacement metal gate process.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference is relevant to the "gate structure" aspect of US9318609B2, particularly if the gate structure is a metal gate (Claim 3) and if the epitaxial layer forms part of the source/drain regions. It could potentially anticipate Claim 3 and aspects of Claims 1, 5, and 10 if the raised source/drain regions are formed epitaxially.

  10. US20070108528A1

    • Full Citation: US20070108528A1 - Sram cell
    • Publication Date: 2007-05-17 (Priority Date: 2005-11-15)
    • Brief Description: This publication generally describes an SRAM cell.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): Without further detail on the SRAM cell's specific construction, it's hard to assess direct anticipation. If the SRAM cell uses FinFETs with similar structural characteristics to US9318609B2, it could potentially anticipate elements of claims 1, 9, and 10.

  11. US20070158756A1

    • Full Citation: US20070158756A1 - Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement
    • Publication Date: 2007-07-12 (Priority Date: 2006-01-12)
    • Brief Description: This publication directly concerns a "Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement," making it highly relevant to the FinFET device of US9318609B2.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a highly relevant reference. It could potentially anticipate most structural claims of US9318609B2, especially Claims 1, 5, 9, and 10, given its focus on FinFET arrangements and their production. The specific details of how the isolation structure and epitaxial layer are formed and their relative heights would be crucial for determining exact anticipation.

  12. US7247887B2

    • Full Citation: US7247887B2 - Segmented channel MOS transistor
    • Publication Date: 2007-07-24 (Priority Date: 2005-07-01)
    • Brief Description: This patent describes a segmented channel MOS transistor.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): If the "segmented channel" involves structures akin to fin structures or if the segmentation impacts how strain is applied, this could be relevant to claims concerning the fin structure and epitaxial layer (Claims 1, 5, 10).

  13. US7250658B2

    • Full Citation: US7250658B2 - Hybrid planar and FinFET CMOS devices
    • Publication Date: 2007-07-31 (Priority Date: 2003-06-26)
    • Brief Description: This patent describes hybrid planar and FinFET CMOS devices, showing the integration of both types of transistors.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This patent is relevant to the general field of FinFETs and their integration. Claims 1, 9, and 10 of US9318609B2, relating to the FinFET structure, could be anticipated depending on the specific FinFET configuration disclosed.

  14. US7309626B2

    • Full Citation: US7309626B2 - Quasi self-aligned source/drain FinFET process
    • Publication Date: 2007-12-18 (Priority Date: 2005-11-15)
    • Brief Description: This patent details a "quasi self-aligned source/drain FinFET process," directly addressing FinFET fabrication and source/drain regions where epitaxial structures are typically formed.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a highly relevant reference, particularly to Claims 1, 5, 9, and 10 of US9318609B2, as it describes a FinFET process involving source/drain regions, which often incorporate epitaxial growth for strain. The specific arrangement of the isolation structure and epitaxial layer relative to the gate would be key to determining anticipation.

  15. US7352034B2

    • Full Citation: US7352034B2 - Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
    • Publication Date: 2008-04-01 (Priority Date: 2005-08-25)
    • Brief Description: This patent focuses on integrating damascene-body FinFETs and planar devices on a common substrate.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference is relevant to FinFET structures and their integration. Claims 1, 9, and 10, which describe the FinFET structure, could be anticipated if the damascene-body FinFETs include similar isolation and epitaxial arrangements as claimed in US9318609B2.

  16. US20080157208A1

    • Full Citation: US20080157208A1 - Stressed barrier plug slot contact structure for transistor performance enhancement
    • Publication Date: 2008-07-03 (Priority Date: 2006-12-29)
    • Brief Description: This publication describes a stressed barrier plug slot contact structure for enhancing transistor performance, which relates to stress application in transistors.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference is relevant to the concept of applying stress for performance enhancement, which is a goal of US9318609B2. Depending on how the stress is applied and its interaction with the fin and epitaxial structures, it could potentially anticipate aspects of claims 1, 5, 8, and 10.

  17. US7470570B2

    • Full Citation: US7470570B2 - Process for fabrication of FinFETs
    • Publication Date: 2008-12-30 (Priority Date: 2006-11-14)
    • Brief Description: This patent explicitly covers a "Process for fabrication of FinFETs."
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a very relevant reference, as it describes FinFET fabrication. While US9318609B2 primarily claims a device, the described device is a product of a fabrication process. This reference could anticipate the structural features of Claims 1, 5, 9, and 10 if its FinFET fabrication process naturally leads to a device with the claimed characteristics.

  18. US7525160B2

    • Full Citation: US7525160B2 - Multigate device with recessed strain regions
    • Publication Date: 2009-04-28 (Priority Date: 2005-12-27)
    • Brief Description: This patent describes a "multigate device with recessed strain regions." This is highly pertinent given US9318609B2's focus on fin structures (a type of multigate device) and epitaxial layers for strain.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a highly relevant reference. "Multigate device" encompasses FinFETs, and "recessed strain regions" directly relates to the epitaxial layer formed in recesses to induce strain as claimed in US9318609B2 (Claims 1, 5, 8, 10). The specific configuration of the recessed regions and how they interact with the isolation and gate structures would be critical for assessing direct anticipation of these claims.

  19. US7531437B2

    • Full Citation: US7531437B2 - Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material
    • Publication Date: 2009-05-12 (Priority Date: 2004-09-30)
    • Brief Description: This patent describes a method for forming metal gate electrodes using sacrificial materials, which is consistent with the replacement metal gate (RMG) process mentioned in US9318609B2.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference is relevant to Claim 3 of US9318609B2, which specifies a metal gate structure. It could potentially anticipate the existence of a metal gate within a FinFET structure, particularly if the described method could be applied to FinFETs.

  20. US20090124097A1

    • Full Citation: US20090124097A1 - Method of forming narrow fins in finfet devices with reduced spacing therebetween
    • Publication Date: 2009-05-14 (Priority Date: 2007-11-09)
    • Brief Description: This publication describes a method for forming narrow fins in FinFET devices with reduced spacing, directly related to the fin structure.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a relevant reference for FinFET fabrication, especially concerning the fin structure. It could potentially anticipate Claim 1 and related claims (9, 10) of US9318609B2, depending on the specific characteristics of the fins and their integration with other components.

  21. US7569857B2

    • Full Citation: US7569857B2 - Dual crystal orientation circuit devices on the same substrate
    • Publication Date: 2009-08-04 (Priority Date: 2006-09-29)
    • Brief Description: This patent describes dual crystal orientation circuit devices, which can influence how strain is applied and its effects on carrier mobility.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference touches upon crystal orientation, which is fundamental to strain engineering in semiconductors. While not directly describing the FinFET structure of US9318609B2, it could be relevant to the underlying principles of applying stress for carrier mobility enhancement (Claims 8, 10) if the epitaxial layer's properties are linked to crystal orientation.

  22. US20090242964A1

    • Full Citation: US20090242964A1 - Non-volatile memory device
    • Publication Date: 2009-10-01 (Priority Date: 2006-04-26)
    • Brief Description: This publication describes a non-volatile memory device.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): Without specific details of the non-volatile memory device's construction, it's difficult to assess direct anticipation. If it utilizes FinFET structures with elements similar to US9318609B2, it could potentially anticipate certain claims (e.g., 1, 9, 10).

  23. US20090269916A1

    • Full Citation: US20090269916A1 - Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges
    • Publication Date: 2009-10-29 (Priority Date: 2008-04-28)
    • Brief Description: This publication describes methods for fabricating memory cells with fin structures having specific top surface and corner profiles.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a relevant reference for FinFET fabrication, specifically regarding the fin structure's geometry. It could potentially anticipate Claim 1 of US9318609B2 regarding the fin structure itself, particularly if the fin's shape impacts the integration of the isolation and epitaxial layers.

  24. US20100048027A1

    • Full Citation: US20100048027A1 - Smooth and vertical semiconductor fin structure
    • Publication Date: 2010-02-25 (Priority Date: 2008-08-21)
    • Brief Description: This publication describes a smooth and vertical semiconductor fin structure, focusing on the quality and profile of the fin.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference focuses on the characteristics of the fin structure, directly relevant to Claim 1 of US9318609B2. It could potentially anticipate aspects of the fin structure's definition.

  25. US20100072553A1

    • Full Citation: US20100072553A1 - METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE
    • Publication Date: 2010-03-25 (Priority Date: 2008-09-23)
    • Brief Description: This publication describes a metal gate stress film for mobility enhancement in FinFET devices. This is highly relevant as it combines FinFETs, metal gates, and stress application.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a highly relevant reference. It combines several key elements of US9318609B2: FinFET devices, metal gates (Claim 3), and mobility enhancement through stress. It could potentially anticipate Claims 1, 3, 5, 8, 9, and 10 of US9318609B2, especially if the "stress film" functions similarly to the epitaxial layer in applying stress and its integration with the gate and fin is comparable.

  26. US20100144121A1

    • Full Citation: US20100144121A1 - Germanium FinFETs Having Dielectric Punch-Through Stoppers
    • Publication Date: 2010-06-10 (Priority Date: 2008-12-05)
    • Brief Description: This publication describes Germanium FinFETs with dielectric punch-through stoppers, indicating the use of different semiconductor materials in FinFETs.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This reference is relevant for FinFETs using different materials, such as Germanium, which relates to the composition of the epitaxial layer (Claim 8). It could potentially anticipate the use of specific materials in FinFET structures, and elements of Claim 1, 5, and 10.

  27. US20100167506A1

    • Full Citation: US20100167506A1 - Inductive plasma doping
    • Publication Date: 2010-07-01 (Priority Date: 2008-12-31)
    • Brief Description: This publication describes inductive plasma doping, a semiconductor manufacturing process.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): Similar to US20060099830A1, this reference is focused on a specific manufacturing technique. It is unlikely to directly anticipate the structural claims of US9318609B2 (Claims 1, 5, 10).

  28. US20120193713A1

    • Full Citation: US20120193713A1 - FinFET device having reduce capacitance, access resistance, and contact resistance
    • Publication Date: 2012-08-02 (Priority Date: 2011-01-31)
    • Brief Description: This publication describes a FinFET device designed to reduce capacitance, access resistance, and contact resistance.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a relevant reference for FinFET device characteristics. It could potentially anticipate elements of Claim 1, 5, 9, and 10 of US9318609B2, particularly if the design features described to reduce resistance and capacitance involve similar fin, isolation, and contact structures.

  29. US8765533B2

    • Full Citation: US8765533B2 - Fin-like field effect transistor (FinFET) channel profile engineering method and associated device
    • Publication Date: 2014-07-01 (Priority Date: 2012-12-04)
    • Brief Description: This patent describes a FinFET channel profile engineering method and the associated device, focusing on shaping the channel region of FinFETs.
    • Potential Anticipated Claim(s) (under 35 U.S.C. § 102): This is a highly relevant reference, especially to Claim 1 of US9318609B2, as it focuses on FinFET channel profiles. The specific engineering of the channel could involve aspects of the fin structure and how it interfaces with the gate and potentially the epitaxial layer. It could also anticipate elements of Claims 5 and 10 depending on whether the channel profile engineering involves similar recessed regions or epitaxial growth.

Generated 5/26/2026, 6:47:46 PM