Obviousness

To analyze the obviousness of US patent 9318609 under 35 U.S.C. § 103, it's necessary to consider the "person having ordinary skill in the art" (PHOSITA) and what would have been obvious to them at the time of the invention, given the prior art. The PHOSITA is a hypothetical person with ordinary skill, ordinary creativity, and ordinary knowledge in the relevant technical field, who is presumed to have known all relevant prior art at the time of the invention. This person is not a genius, nor are they an inventor; they are expected to follow conventional wisdom and apply known techniques in a predictable manner.

The stated objective of US9318609 is to provide a semiconductor device with an epitaxial layer such that stress imposed on the channel region can be increased, and to prevent the formation of void defects in the epitaxial layer by reducing the height of the isolation structure at the sides of the gate structure, thus preventing the epitaxial structure from being sealed during growth.

The patent itself lists 29 prior art documents. For a thorough obviousness analysis, each independent claim would need to be considered against combinations of these references. However, without a detailed breakdown of the specific teachings of each of the 29 cited prior art references, a complete obviousness analysis with specific combinations is not possible. The patent text only provides titles and publication details for these references, not their full content.

Therefore, this analysis will identify common themes in the prior art, and suggest how a PHOSITA might combine elements to achieve the claimed invention, based on the abstract and description of US9318609, and general knowledge in the field.

Level of Ordinary Skill in the Art (PHOSITA) for US9318609

For US9318609, the PHOSITA would be an individual with knowledge and experience in semiconductor device fabrication, particularly in the areas of FinFET technology, crystal strain engineering, and epitaxial growth processes. This would likely include:

• Educational Level: A bachelor's or master's degree in electrical engineering, materials science, or a related field, potentially with practical experience in semiconductor manufacturing or research.
• Technical Understanding: Familiarity with MOSFET and FinFET structures, shallow trench isolation (STI), gate-last processes (including high-k last), and the principles of applying strain to semiconductor channels to enhance carrier mobility.
• Process Knowledge: Understanding of various semiconductor fabrication techniques, including etching (wet and dry), deposition, photolithography, and epitaxial growth (e.g., MBE, selective epitaxial growth).
• Problem Solving: An awareness of common challenges in advanced semiconductor manufacturing, such as defect formation (e.g., void defects in epitaxial layers) and methods to mitigate them.

General Obviousness Considerations (based on common problems and solutions in the art)

The background of US9318609 explicitly states that "crystal strain technology has been developed" to improve device performance by increasing carrier mobility. It also acknowledges that "attempts have been made to use a strained silicon layer as a part of MOS transistors in which an epitaxial silicon germanium (SiGe) structure or an epitaxial silicon carbide (SiC) structure is formed". The core problem addressed by the patent is the formation of "void defects in the epitaxial layer" due to the high aspect ratio of epitaxial layers in continuously shrinking devices, which reduces the desired stress on the channel region. The solution proposed is to reduce the height of the isolation structure at the sides of the gate, preventing the epitaxial structure from being sealed during growth and thus avoiding voids.

Given this context, a PHOSITA would be motivated to address the problem of void defects in epitaxial layers used for strain engineering. If prior art references individually disclose elements of the claimed invention, and there's a recognized problem that the combination would solve, or if the combination simply yields predictable results, it could be considered obvious.

Potential Combinations of Prior Art (Hypothetical)

Without access to the full text of the 29 cited prior art references, it is difficult to identify precise combinations. However, based on the general descriptions and the problem/solution presented in US9318609, here are some hypothetical scenarios for obviousness, assuming typical disclosures in the cited prior art:

Assumption 1: Prior art discloses FinFETs with strained epitaxial source/drain regions, and separate prior art discloses recessed isolation structures.

• Scenario: Many of the cited prior art documents relate to FinFETs, strained channels, and semiconductor fabrication. For example, US20040195624A1 is titled "Strained silicon fin field effect transistor," US20060286729A1 is "Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate," and US7525160B2 is "Multigate device with recessed strain regions." It is highly probable that several of the cited references disclose the general concept of forming a fin structure, an isolation structure, a gate structure, and strained epitaxial regions in FinFETs to enhance performance.
• Combination: If a primary reference (e.g., US20040195624A1) discloses a FinFET device with a fin structure, an isolation structure, a gate structure, and an epitaxial layer for strain, but does not explicitly show the recessed isolation structure to prevent voids, a PHOSITA would look for solutions to common problems in epitaxial growth.
• Motivation: The problem of void defects in high-aspect-ratio epitaxial layers is explicitly stated in US9318609 as an "important issue". A PHOSITA, aware of this known problem, would be motivated to find ways to improve epitaxial growth quality. If other prior art references (not explicitly detailed here, but presumed to exist within the 29 cited) teach methods of recessing isolation structures to improve subsequent deposition or growth processes, or to alter the geometry for improved filling, a PHOSITA would be motivated to combine these teachings. For example, if a reference like US7531437B2 ("Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material") or other general fabrication method patents discuss modifying trench isolation or dielectric heights, a PHOSITA would understand the utility of such modifications for different subsequent steps. Reducing the height of the isolation structure to create a larger opening for epitaxial growth and prevent sealing would be a predictable modification to address the known void defect problem.
• Obviousness: The combination would be obvious because the primary reference provides the basic FinFET structure with epitaxial strain, and the secondary reference provides a known technique (recessing isolation structures) that a PHOSITA would apply to solve a recognized problem (void defects in epitaxial growth) in a predictable way.

Assumption 2: Prior art discusses the importance of avoiding sealing during epitaxial growth in other contexts.

• Scenario: The patent highlights that "since the epitaxial structure is not sealed during the epitaxial growth process, the void defects may be also avoided as a result". This suggests that avoiding sealing during epitaxial growth was a known desideratum in the art.
• Combination: If the prior art (e.g., some of the fabrication method patents listed like US6492216B1 "Method of forming a transistor with a strained channel" or US20050051825A1 "Semiconductor device and manufacturing method thereof") generally discusses epitaxial growth challenges and the importance of open geometries, even if not specifically in the context of recessed STI in FinFETs.
• Motivation: A PHOSITA, encountering the problem of void defects in FinFET epitaxial regions, would recognize that preventing the sealing of the growth area could solve this problem. If general epitaxial growth literature (which would be known to a PHOSITA) taught that open geometries prevent sealing and improve fill, the idea of recessing the adjacent isolation structure to achieve this would be a logical and predictable step for the PHOSITA.
• Obviousness: The combination would be obvious because the general principle of avoiding sealing during epitaxial growth is known, and applying a known structural modification (recessing the isolation) to achieve this known beneficial outcome in a FinFET context would be within the ordinary skill of the art.

Assumption 3: Prior art discloses variable height isolation structures for different purposes, and other prior art discloses epitaxial strain in FinFETs.

• Scenario: Claim 1 specifically states that "the isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, and the first top surface is higher than the second top surface." It's possible that prior art documents, such as those related to STI processes (e.g., some general semiconductor process patents), disclose varying the height of isolation structures for various reasons (e.g., to reduce capacitance, adjust stress, or facilitate subsequent processing steps).
• Combination: A PHOSITA would be aware of various methods for creating differential heights in isolation structures. When combined with the known need for strained epitaxial layers in FinFETs (from references like US20040195624A1 or US20100072553A1 "METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE"), and the known problem of void defects, the PHOSITA would be motivated to combine these elements.
• Motivation: The motivation would stem from the recognized problem of void defects during epitaxial growth in high-aspect-ratio structures and the understanding that creating a more open geometry could alleviate this. Adjusting the isolation structure height is a known parameter in semiconductor fabrication, and a PHOSITA would predictably manipulate this to optimize epitaxial fill and stress, particularly in light of known issues like void formation.
• Obviousness: The combination would be obvious as it involves applying a known structural variation (differential isolation height) to a known device (FinFET with strained epitaxy) to solve a known problem (epitaxial voids) using a predictable approach (creating more open space for growth).

Conclusion

A definitive obviousness analysis requires full access to and detailed review of the 29 prior art references cited in US9318609. However, based on the problem statement and solution described in the patent, it is likely that a person having ordinary skill in the art would have been motivated to combine existing knowledge in FinFET fabrication, strain engineering, and epitaxial growth techniques. The core inventive step, as described, revolves around the specific geometry of recessing the isolation structure to prevent void defects during epitaxial growth. If prior art teaches FinFETs with strained epitaxial regions and also teaches methods for recessing isolation structures (perhaps for other purposes, but with recognizable benefits for deposition/growth), or if it broadly discusses avoiding sealing during epitaxial processes, then the combination to achieve the claimed invention would likely be considered obvious. The height difference between the first and second top surfaces of the isolation structure, ranging from 100 to 250 Angstroms (Claim 2), also appears to be a matter of routine optimization for a PHOSITA once the concept of recessing the isolation for void prevention is understood.