Patent 9117909

Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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US Patent 9117909B2, titled "Non-planar transistor," was granted on August 25, 2015, from an application filed on August 28, 2014, with a priority date of April 16, 2013. The patent describes a non-planar transistor structure and a method for forming fin structures with improved critical dimension (CD) uniformity, particularly by employing a two-step etching process and a selective removal of fin structures in certain regions to mitigate "dense-isolation effect" or "micro-loading effect" issues.

The most relevant prior art for US patent 9117909B2, particularly for its independent claim (Claim 1), would be references that disclose core FinFET structures, fin formation techniques, and methods addressing uniformity or specific fin sidewall profiles. The following are selected patent citations from US9117909B2, along with a brief description and an assessment of their potential to anticipate its claims under 35 U.S.C. § 102.

Analysis of Cited Prior Art:

  1. US20040195624A1

    • Full Citation: US20040195624A1 (Strained silicon fin field effect transistor)
    • Publication/Filing Date: Publication: 2004-10-07 / Priority: 2003-04-04
    • Brief Description: This patent application describes a strained silicon fin field effect transistor, which inherently involves a non-planar transistor structure with a fin. The focus on "strained silicon" suggests methods for enhancing performance within such structures.
    • Potential Anticipation (Claim 1): This reference likely anticipates the broad concept of a "non-planar transistor" comprising a "fin structure," a "conductive layer" (gate), and a "gate dielectric layer." Depending on its specific disclosures, it may also describe "trenches" and "insulation layers" to define the fin. However, it is less likely to explicitly disclose the specific combination of "shallow trenches" and a "deeper trench" in different regions, or the precise "upper portion having a substantially vertical sidewall and a lower portion having a tilted sidewall" as claimed in US9117909B2. The specific method of forming these features with improved CD uniformity is also a distinguishing aspect of 9117909.

  2. US6921963B2

    • Full Citation: US6921963B2 (Narrow fin FinFET)
    • Publication/Filing Date: Publication: 2005-07-26 / Priority: 2003-01-23
    • Brief Description: This patent details a FinFET with a "narrow fin," indicating a focus on manufacturing and controlling the dimensions of the fin structure.
    • Potential Anticipation (Claim 1): Similar to US20040195624A1, this patent likely anticipates the fundamental FinFET structure, including the "substrate," "fin structure," "gate dielectric layer," and "conductive layer." The emphasis on "narrow fin" suggests methods for precise fin definition, which could involve trench formation and isolation. However, whether it specifically teaches the combination of shallow and deep trenches in active/isolation regions, the distinct upper/lower fin sidewall profiles, or the specific "level with" insulation layer feature of US9117909B2's Claim 1 would require a full review of its specifications and drawings.

  3. US20070158756A1

    • Full Citation: US20070158756A1 (Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement)
    • Publication/Filing Date: Publication: 2007-07-12 / Priority: 2006-01-12
    • Brief Description: This application covers both a FinFET transistor arrangement and its production method, suggesting it addresses the fabrication processes for such devices.
    • Potential Anticipation (Claim 1): Given its focus on both the FinFET arrangement and its production method, this reference is highly likely to disclose the structural elements of a FinFET, potentially including the "fin structure," "trenches," and "isolation layers." The methods might involve etching steps to define the fins. To anticipate Claim 1 of US9117909B2, it would need to explicitly teach the differentiation between shallow and deep trenches based on active/isolation regions, the specific sidewall profiles (vertical upper, tilted lower), and the precise leveling of the insulation layer.

  4. US20090124097A1

    • Full Citation: US20090124097A1 (Method of forming narrow fins in finfet devices with reduced spacing therebetween)
    • Publication/Filing Date: Publication: 2009-05-14 / Priority: 2007-11-09
    • Brief Description: This patent application is directly relevant to FinFET fabrication, focusing on methods for creating "narrow fins" with "reduced spacing," which implies addressing uniformity and density issues.
    • Potential Anticipation (Claim 1): This reference explicitly deals with forming fins in FinFETs, making it very relevant to the core subject matter of US9117909B2. It would likely disclose a "substrate," "fin structures," and "trenches" that define them. While it aims for narrow fins and reduced spacing, whether it teaches the specific multi-depth trench structure (shallow and deep based on regions), the distinct fin sidewall geometries (vertical upper, tilted lower), and the precise insulation layer leveling as specified in US9117909B2's Claim 1 is not apparent from the title alone. The method aspects regarding CD uniformity might be similar in goal but potentially different in specific steps.

  5. US20090269916A1

    • Full Citation: US20090269916A1 (Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges)
    • Publication/Filing Date: Publication: 2009-10-29 / Priority: 2008-04-28
    • Brief Description: This application describes methods for fabricating fin structures, but with a specific focus on "semicircular top surfaces and rounded top corners and edges."
    • Potential Anticipation (Claim 1): This reference clearly teaches the fabrication of "fin structures" and implicitly a "non-planar transistor" structure. However, the fin geometry described (semicircular top, rounded corners/edges) is different from the "upper portion having a substantially vertical sidewall and a lower portion having a tilted sidewall" specified in Claim 1 of US9117909B2. While it addresses fin shaping, its specific geometry likely does not anticipate the precise fin profile of US9117909B2.

  6. US20100048027A1

    • Full Citation: US20100048027A1 (Smooth and vertical semiconductor fin structure)
    • Publication/Filing Date: Publication: 2010-02-25 / Priority: 2008-08-21
    • Brief Description: This patent application focuses on achieving a "smooth and vertical semiconductor fin structure."
    • Potential Anticipation (Claim 1): This reference is highly relevant due to its explicit mention of a "vertical semiconductor fin structure," which directly relates to the "upper portion having a substantially vertical sidewall" in US9117909B2's Claim 1. However, Claim 1 of US9117909B2 also specifies a "lower portion having a tilted sidewall" and the differentiated trench depths in active and isolation regions, which might not be present in US20100048027A1. If US20100048027A1 only teaches a uniformly vertical fin, it would not anticipate the combination of vertical and tilted sidewalls.

  7. US8110466B2

    • Full Citation: US8110466B2 (Cross OD FinFET patterning)
    • Publication/Filing Date: Publication: 2012-02-07 / Priority: 2009-10-27
    • Brief Description: This patent describes patterning techniques for FinFETs, implying methods to define the fin structures and isolation regions. "Cross OD" likely refers to patterning over active device (OD) regions.
    • Potential Anticipation (Claim 1): As a FinFET patterning patent, it would involve forming fin structures on a "substrate" and separating them with "trenches" filled with "insulation layer." This directly addresses several elements of Claim 1. However, specific details like the "shallow trenches" vs. "deep trench," the distinct fin sidewall profiles (vertical upper, tilted lower), and the precise "level with" insulation layer in different regions would need to be explicitly present in US8110466B2 to anticipate Claim 1 of US9117909B2. The inventive step in 9117909 regarding CD uniformity through selective removal and two-step etching is also a key differentiating factor.

  8. US20140035066A1

    • Full Citation: US20140035066A1 (Non-Planar FET and Manufacturing Method Thereof)
    • Publication/Filing Date: Publication: 2014-02-06 / Priority: 2012-07-31
    • Brief Description: This application broadly covers both a non-planar FET structure and its manufacturing method, making it highly relevant to the subject matter of US9117909B2. Its priority date (2012-07-31) is before that of US9117909B2 (2013-04-16), making it statutory prior art.
    • Potential Anticipation (Claim 1): Given its broad title covering both structure and manufacturing method, this reference likely discloses a "non-planar transistor" with a "fin structure" on a "substrate," defined by "trenches" and isolated by an "insulation layer," and including "gate dielectric" and "conductive layers." The crucial question for anticipation of Claim 1 of US9117909B2 lies in whether US20140035066A1 explicitly teaches all the specific features: a plurality of shallow trenches in an active region, a deep trench in an isolation region (deeper than shallow), a protruding structure with upper vertical and lower tilted sidewalls, an insulation layer whose upper surface in the shallow trenches is level with that in the deep trench, and a fin structure protruding over the insulation layer. The detailed method for achieving fin uniformity and specific sidewall profiles as described in US9117909B2 would be a key area of differentiation.

  9. US8946829B2

    • Full Citation: US8946829B2 (Selective fin-shaping process using plasma doping and etching for 3-dimensional transistor applications)
    • Publication/Filing Date: Publication: 2015-02-03 / Priority: 2011-10-14
    • Brief Description: This patent focuses on a "selective fin-shaping process" using plasma doping and etching for 3D transistors, which are FinFETs. This directly relates to forming the desired fin geometry.
    • Potential Anticipation (Claim 1): This reference is very relevant due to its focus on "selective fin-shaping" for 3D transistors. It would likely disclose a "substrate," "fin structures," and methods involving "etching." The term "selective fin-shaping" could potentially encompass techniques to create varied sidewall profiles or fin dimensions. For anticipation of Claim 1 of US9117909B2, it would need to explicitly describe the combination of shallow and deep trenches in active/isolation regions, the specific upper vertical/lower tilted sidewall profile, and the precise leveling of the insulation layer as defined in Claim 1. The novelty of 9117909 also lies in its specific approach to achieving CD uniformity.

Relationship with US8853015B1:

  • US8853015B1 (Method of forming a FinFET structure) is explicitly identified as the parent application (Divisional of application Ser. No. 13/863,393 filed Apr. 16, 2013) for US9117909B2.
  • Publication/Filing Date: Publication: 2014-10-07 / Priority: 2013-04-16
  • Brief Description: This patent describes a method of forming a FinFET structure. As a parent application, it would cover related inventive concepts in the FinFET fabrication process.
  • Potential Anticipation (Claim 1): As a direct parent application with the same priority date, US8853015B1 is not considered "prior art" under 35 U.S.C. § 102 for US9117909B2. Instead, it represents a related invention from the same inventive entity. The claims of US9117909B2 are likely directed to specific structural aspects or further refinements of the methods described in US8853015B1. The present invention (US9117909B2) claims a "non-planar transistor" structure, while the parent (US8853015B1) claims a "method of forming a FinFET structure." Therefore, while the subject matter is highly related, they are distinct types of claims.

Summary of Anticipation:

Generally, the cited FinFET-related prior art anticipates the broad concept of a non-planar transistor, fin structures, and their basic fabrication methods. However, the specific combination of elements claimed in US9117909B2's independent Claim 1, particularly:

  • The definition of distinct "first region," "second region encompassing the first region," and "third region encompassing the second region" on the substrate (from the abstract/description, this translates to active and isolation regions with specific trench depths).
  • The plurality of "shallow trenches" in the active region defining a protruding structure.
  • The "deep trench" in the isolation region, being "deeper than the shallow trenches."
  • The "protruding structure" having a specific "upper portion having a substantially vertical sidewall and a lower portion having a tilted sidewall."
  • The "insulation layer" having an "upper surface... level with that in the deep trench."
  • And the method steps detailed in the specification to achieve consistent Critical Dimension (CD) uniformity, for example, by removing fin structures in the second region to avoid "dense-isolation effect" or "micro-loading effect."

These detailed structural features, especially the precise interplay of different trench depths, specific fin sidewall profiles, and the leveled insulation layer across different regions, are key to the novelty of US9117909B2. While prior art shows various FinFETs and methods, it is unlikely from their titles and brief descriptions that any single reference explicitly teaches all these specific elements in combination to fully anticipate Claim 1. A thorough anticipation analysis would require a detailed claim chart comparing each element of Claim 1 of US9117909B2 against the full disclosure of each cited patent.

Generated 5/23/2026, 6:49:04 PM