Obviousness

Obviousness Analysis of US Patent 9117909 under 35 U.S.C. § 103

To determine obviousness under 35 U.S.C. § 103, we must consider whether the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (POSITA). This analysis requires identifying a motivation to combine prior art references to achieve the claimed invention with a reasonable expectation of success. The motivation to combine can come from the knowledge of those skilled in the art, from the prior art references themselves, or from the nature of the problem to be solved.

The core inventive concept of US Patent 9117909, particularly as laid out in Claim 1, revolves around a non-planar transistor (FinFET) structure featuring fin uniformity and precisely controlled sidewall profiles (vertical upper portion, tilted lower portion) achieved through a specific multi-step etching and fin removal process, and the differentiated depth of trenches in active and isolation regions.

Challenges in FinFET Manufacturing (Problem to be Solved)

At the time of the invention's priority date (April 16, 2013), FinFET technology was actively developing, and manufacturers faced significant challenges, particularly concerning fin uniformity and control over fin dimensions. The abstract of US9117909 explicitly states that a problem to be overcome is "poor CD uniformity of the fin structures of Fin-FETs." The detailed description further elaborates on issues like "dense-isolation effect" or "micro-loading effect" leading to variations in fin width. These were known problems in the industry, driving innovation in FinFET fabrication.

Potential Prior Art Combinations and Motivations

The patent lists numerous prior art references, which can be broadly categorized as related to FinFET structures, manufacturing methods, and etching techniques. We will analyze how a POSITA would have been motivated to combine certain references to arrive at the claimed invention, focusing on Claim 1.

Claim 1 Breakdown:

Claim 1 describes a non-planar transistor comprising:

• A substrate with active and isolation regions.
• Shallow trenches in the active region defining a protruding structure with an upper vertical sidewall portion and a lower tilted sidewall portion.
• A deep trench in the isolation region, deeper than the shallow trenches, with a shoulder portion.
• An insulation layer in all trenches, level across all, leaving a fin structure protruding from the insulation.
• A conductive layer and gate dielectric layer on the fin structure.

Combination 1: Addressing Fin Uniformity and Sidewall Profile (Core of the Invention)

• Prior Art References:

  • US8310013B2 (Lin et al.): This patent, filed in August 2011, discusses problems associated with FinFET fabrication, specifically the inability of conventional methods to provide varied profiles, such as a square profile, of fin structure facets. It notes that "simply changing various process settings has proved incapable of significantly improving the ability to fabricate varied profiles." This directly highlights the problem of controlling fin profiles.
  • US20100048027A1 (International Business Machines Corporation): Titled "Smooth and vertical semiconductor fin structure," this publication suggests approaches for achieving desired fin sidewall characteristics.
  • General knowledge in the art: The "dense-isolation effect" or "micro-loading effect" were recognized challenges in semiconductor manufacturing leading to non-uniform etching and fin critical dimension (CD) variations.

• Motivation to Combine: A POSITA, facing the known challenges of poor CD uniformity and difficulty in achieving desired fin profiles in FinFETs (as highlighted by Lin et al. and industry knowledge), would be motivated to develop fabrication methods that offer better control over fin dimensions and sidewall shapes. The objective would be to improve device performance and yield, which are universal and common-sensical motivations in semiconductor manufacturing.

  The method described in US9117909 addresses these issues by:

  1. Initially forming first trenches and first protruding structures.
  2. Removing the first protruding structures in the second (isolation) region. This step is crucial for mitigating dense-isolation or micro-loading effects that would otherwise lead to wider fins in this region. The patent explicitly states this is done "to keep the CD uniformity of the fin structure 330."
  3. Deepening the remaining first trenches in a second etching step, which allows for better control of the fin's final shape. The patent notes that the lower portion can have tilted sidewalls due to a faster etching rate in the second step, while the upper portion retains vertical sidewalls, forming the actual fin structure. This two-step etching process (initial trenching, selective fin removal, then deepening) provides a more refined control over the fin's CD and profile compared to a single etching step that could result in tapered sidewalls.

  Therefore, a POSITA, motivated by the need for uniform and well-defined FinFET structures, would consider combining etching techniques known to produce smooth and vertical sidewalls (like those hinted at in US20100048027A1) with an understanding of how to counteract loading effects, potentially through selective removal or differential etching strategies. The explicit teaching in US9117909 to remove fins in certain regions to achieve uniformity directly addresses a known problem in the art.

Combination 2: Differentiated Trench Depths for Active and Isolation Regions

• Prior Art References:

  • US8853015B1 (United Microelectronics Corp.): This patent, a related parent application with the same priority date and assignee, is titled "Method of forming a FinFET structure." While not directly cited as prior art against US9117909 in the patent document itself, it represents related work by the same entity at the same time and could be considered relevant for understanding the knowledge of the inventors or the immediate prior art landscape.
  • US20140035066A1 (Tsai et al.): Titled "Non-Planar FET and Manufacturing Method Thereof," this publication, filed July 2012, further illustrates the ongoing development in FinFET manufacturing techniques.
  • General knowledge of STI (Shallow Trench Isolation) and deep trench isolation: The use of STI to isolate active regions in semiconductor devices was well-established. Different depths of trenches for isolation and active areas would be a known concept to a POSITA.

• Motivation to Combine: The concept of having different trench depths for isolation regions versus active regions is a fundamental aspect of semiconductor device fabrication, particularly for achieving effective electrical isolation and optimizing device performance. A POSITA would be motivated to integrate deeper trenches in isolation regions to ensure robust electrical isolation, especially as device dimensions shrink.

  Claim 1 of US9117909 specifies "a deep trench disposed in the substrate in the isolation region, wherein the deep trench is deeper than the shallow trenches." This differentiation is a logical engineering choice to enhance isolation, a common goal in device design. The teaching that "the insulation layer in the shallow trenches is level with that in the deep trench" further indicates a practical approach to planarization after trench filling, which is also a common objective in semiconductor processing. The "shoulder portion" of the deep trench could arise from specific etching profiles or subsequent processing steps, which a POSITA would be familiar with when creating trenches of varying depths.

Overall Obviousness Conclusion:

While US9117909 presents a specific combination of steps to achieve fin uniformity and controlled sidewall profiles, a POSITA, motivated by well-known challenges in FinFET manufacturing such as achieving critical dimension (CD) uniformity and desirable fin profiles, and the general need for effective isolation, would have found motivation to combine existing knowledge of multi-step etching, selective material removal, and differential trench depths. The patent itself highlights the "dense-isolation effect" and "micro-loading effect" as problems, and the solutions it proposes (selective fin removal and two-step etching for sidewall control) would be considered logical advancements by a POSITA seeking to overcome these recognized issues.

Specifically, the combination of a FinFET structure (known from various references like US8310013B2), techniques for achieving controlled etching profiles (as broadly discussed in the prior art for "smooth and vertical" structures), and the well-understood need for distinct isolation features (deep trenches for isolation, shallow trenches for active areas) with a planarized insulation layer, would likely render Claim 1 obvious. The specific method of removing fins in an intermediate step to ensure uniformity and then deepening the trenches to achieve the desired composite fin shape addresses known problems in a manner that a POSITA would likely contemplate when striving for improved FinFET device quality and uniformity.

It is important to note that merely asserting that references are similar or in the same field is insufficient for an obviousness finding; there must be an articulated reasoning with a rational underpinning for combining them. In this case, the problems addressed by US9117909 (CD uniformity, sidewall control, effective isolation in FinFETs) were prominent in the field, providing a strong motivation for a POSITA to combine known techniques to achieve the claimed structure.