Prior art — US Patent 8947962

To identify the most relevant prior art for US patent 8947962, I will examine its cited patent references. The core innovation of US8947962, as described in Claim 1, is a memory controller that can selectively disable on-die termination (ODT) circuitry on a subset of address and control (RQ) bus signal lines by driving control signals. This selective disabling specifically aims to reduce power consumption and optimize signal integrity.

I will focus on cited patents whose titles or abstracts clearly indicate they deal with on-die termination, dynamic termination, or termination control for address/command signals in memory systems. For each, I will provide the full citation, publication/filing date, a brief description (based on available abstracts), and an assessment of which claims of US8947962 they might potentially anticipate.

Based on the titles provided in US8947962's "Patent Citations" section, the following patents appear to be particularly relevant:

Most Relevant Prior Art for US8947962

US5467455A
- Full Citation: US5467455A - Data processing system and method for performing dynamic bus termination
- Publication Date: 1995-11-14
- Filing Date: 1993-11-03
- Brief Description: This patent describes a data processing system and method that utilizes dynamic bus termination. The termination impedance is switched by the bus master (controller) only when a bus transaction is occurring, thereby conserving power. It is applied to a data bus and aims to reduce power consumption during idle cycles.
- Potential Anticipation: This patent potentially anticipates aspects of Claim 1, particularly the concept of a controller dynamically enabling/disabling termination for power management. It also anticipates the general idea of selective termination (Claim 2) and power saving (Claim 11). However, it focuses on data bus termination rather than on-die termination of address and control (RQ) signals.
WO1998004041A1
- Full Citation: WO1998004041A1 - Programmable dynamic line-termination circuit
- Publication Date: 1998-01-29
- Filing Date: 1996-07-19
- Brief Description: This patent describes a programmable dynamic line-termination circuit that includes a termination resistor and a switch. The switch is controlled by a control signal, allowing the termination to be dynamically enabled or disabled. The termination resistance can also be programmed.
- Potential Anticipation: This reference potentially anticipates the "selectively disable the ODT circuitry" aspect of Claim 1, as well as the dynamic control (Claim 2) and the ability to have different impedance values (Claim 12, 13, 15), but it is general to line termination and does not specify on-die termination for an RQ bus controlled by a memory controller.
WO2000041300A1 (also US6157206A)
- Full Citation: WO2000041300A1 - On-chip termination
- Publication Date: 2000-07-13
- Filing Date: 1998-12-31
- Brief Description: This patent describes a system with on-chip termination (OCT) circuitry. The termination impedance can be adjusted to match the transmission line impedance to reduce signal reflections. While it mentions on-chip termination, the abstract does not explicitly detail dynamic control by a memory controller over address/command signals.
- Potential Anticipation: This patent anticipates the fundamental concept of "on-die termination (ODT) circuitry" as recited in Claim 1. Further analysis of its claims would be needed to determine if it discloses a memory controller that selectively disables this ODT circuitry for a subset of RQ signals.
US6308232B1
- Full Citation: US6308232B1 - Electronically moveable terminator and method for using same in a memory system
- Publication Date: 2001-10-23
- Filing Date: 1999-09-01
- Brief Description: This patent discloses a memory system with an electronically movable terminator. The terminator's position can be adjusted to improve signal integrity, implying dynamic control within a memory system context. It discusses termination in a general bus context, not specifically for address/command signals or on-die.
- Potential Anticipation: This patent could anticipate the concept of dynamic termination in a memory system (related to Claims 1, 2, 18, 19) and the controller's role in optimizing signal integrity. However, it does not specify "on-die termination" of "address and control (RQ) bus" signals or explicit "selective disabling" for power.
US6356106B1
- Full Citation: US6356106B1 - Active termination in a multidrop memory system
- Publication Date: 2002-03-12
- Filing Date: 2000-09-12
- Brief Description: This patent details an active termination scheme for a multidrop memory system where termination is selectively enabled or disabled. It focuses on reducing reflections and power consumption. The termination is described as "active," implying dynamic control, and is specifically for a multidrop memory system.
- Potential Anticipation: This patent is highly relevant and potentially anticipates several claims. It discloses active/dynamic termination in a multidrop memory system, which could cover a "fly-by topology" (Claim 5). It aims to reduce power consumption (Claim 11) and improve signal integrity. Depending on how "active termination" is defined, it could anticipate the selective disabling/enabling of termination in Claim 1 and Claim 2. Further details would be needed to confirm if it applies to on-die termination of address and command signals.
US20030043681A1
- Full Citation: US20030043681A1 - Dram active termination control
- Publication Date: 2003-03-06
- Filing Date: 2001-08-30
- Brief Description: This publication describes a DRAM device with active termination controlled by a termination control signal. The termination is enabled or disabled to improve signal integrity and reduce power. It specifically mentions DRAM and active control.
- Potential Anticipation: This is a strong piece of prior art. It anticipates "active termination" in DRAM, which implies on-die termination. It refers to "termination control," which could be driven by a memory controller. This directly relates to the "selectively disable the ODT circuitry" in Claim 1, as well as enabling (Claim 2), and power savings (Claim 11). The key difference for US8947962 would be the explicit focus on a subset of address and control (RQ) bus signal lines.
US6894691B2
- Full Citation: US6894691B2 - Dynamic switching of parallel termination for power management with DDR memory
- Publication Date: 2005-05-17
- Filing Date: 2002-05-01
- Brief Description: This patent discloses dynamically switching parallel termination to manage power in DDR memory systems. The termination is enabled or disabled based on memory operations, such as active or standby states, to save power.
- Potential Anticipation: This patent is highly relevant, explicitly discussing dynamic switching of termination for power management in DDR memory. This directly addresses the power saving advantage of US8947962 (Claim 11) and the dynamic control aspects (Claims 1, 2, 18, 19). The application to "address and control (RQ) bus" would be a distinguishing factor for US8947962.
US20040100837A1
- Full Citation: US20040100837A1 - On-die termination circuit and method for reducing on-chip DC current, and memory system including memory device having the same
- Publication Date: 2004-05-27
- Filing Date: 2002-11-20
- Brief Description: This publication describes an on-die termination (ODT) circuit that reduces DC current consumption. It includes a switch to enable or disable the ODT circuit, and a control signal manages this switch.
- Potential Anticipation: This is very strong prior art as it explicitly mentions "on-die termination circuit" with a switch to "enable or disable" it using a "control signal," and is aimed at reducing power. This directly anticipates the core elements of Claim 1, including "on-die termination (ODT) circuitry connected to a subset of signal lines," and the ability to "selectively disable the ODT circuitry" via "control signals." The remaining distinction for US8947962 would be the specific application to an "address and control (RQ) bus" and the controller driving the control signals.
US20040228196A1
- Full Citation: US20040228196A1 - Memory devices, systems and methods using selective on-die termination
- Publication Date: 2004-11-18
- Filing Date: 2003-05-13
- Brief Description: This patent describes memory devices, systems, and methods that use selective on-die termination. It enables or disables ODT for specific memory devices or signal lines based on operational needs, such as which device is being accessed, to improve signal integrity and manage power.
- Potential Anticipation: This is also very strong prior art. It explicitly discloses "selective on-die termination" in "memory devices" and "systems" that enables/disables ODT based on operations. This directly anticipates Claim 1 (selective disabling of ODT circuitry), Claim 2 (selective enabling), Claim 11 (power saving), Claim 18 (enablement according to memory operations), and Claim 19 (disabling based on current operations). The specific "address and control (RQ) bus" and "subset of signal lines" (e.g., excluding clock lines as in Claim 8) would be key differentiating features for US8947962.
US7123047B2
- Full Citation: US7123047B2 - Dynamic on-die termination management
- Publication Date: 2006-10-17
- Filing Date: 2004-08-18
- Brief Description: This patent describes a memory system and device with dynamic on-die termination management. It includes a memory controller that issues commands to memory devices to dynamically enable, disable, or adjust the ODT settings to optimize signal integrity across the memory bus.
- Potential Anticipation: This is extremely relevant. It describes "dynamic on-die termination management" by a "memory controller" issuing "commands" to "memory devices" to dynamically "enable, disable, or adjust" ODT. This directly anticipates a broad range of claims: Claim 1 (memory controller selectively disabling ODT), Claim 2 (selectively enabling), Claim 12 (different impedance values), Claim 14 (driving signals after termination), Claim 15 (controlling impedance via control lines), Claim 18 (enabling according to memory operations), and Claim 19 (disabling based on operations). The primary distinction for US8947962 would be the explicit focus on a subset of address and control (RQ) bus signal lines specifically, and the use of "ODT control lines" for disabling, rather than general commands.
US20060146627A1 (Cited by examiner)
- Full Citation: US20060146627A1 - Memory system having multi-terminated multi-drop bus
- Publication Date: 2006-07-06
- Filing Date: 2004-12-31
- Brief Description: This publication describes a memory system with a multi-terminated multi-drop bus. It employs multiple termination units along the bus, which can be selectively enabled or disabled to manage signal reflections in high-speed memory interfaces.
- Potential Anticipation: This patent anticipates the concept of termination in multi-drop bus systems (similar to fly-by topology, Claim 5) and the selective enabling/disabling of multiple termination units (similar to Claim 3). While it doesn't explicitly state "on-die" for address/command signals, it's highly relevant to the overall system context and dynamic termination control within a multi-drop memory environment.

These identified prior art references reveal that the concepts of on-die termination, dynamic termination, and control of termination in memory systems for signal integrity and power saving were known. The novelty of US8947962 appears to reside in the specific combination of these elements, particularly a memory controller selectively disabling on-die termination circuitry in memory devices specifically for a subset of address and control (RQ) bus signal lines by driving ODT control lines. Many of the cited references describe various aspects of dynamic termination, but often for data buses or without the precise control mechanism and specific signal subset of US8947962.