Obviousness

To analyze the obviousness of US patent 8947962 under 35 U.S.C. § 103, we will examine the independent claim (Claim 1) and identify combinations of prior art references that would render its subject matter obvious to a person having ordinary skill in the art (POSITA) at the time of the invention (priority date: December 21, 2006).

Independent Claim 1 Analysis

Claim 1 of US8947962 describes:
"A memory controller configured to be connected to one or more memory devices via an address and control (RQ) bus, wherein:
each of the memory devices have on-die termination (ODT) circuitry connected to a subset of signal lines of the address and control (RQ) bus; and
the memory controller is operable to selectively disable the ODT circuitry in at least one memory device of the one or more memory devices by driving control signals on a plurality of ODT control lines."

The key elements of Claim 1 are:

1. A memory controller.
2. Connected to one or more memory devices via an address and control (RQ) bus.
3. Memory devices having on-die termination (ODT) circuitry.
4. ODT circuitry connected to a subset of signal lines of the RQ bus.
5. The memory controller is operable to selectively disable the ODT circuitry in at least one memory device.
6. By driving control signals on a plurality of ODT control lines.

Obviousness Combination

A combination of prior art references that would render Claim 1 obvious includes:

• US7123047B2 to Intel Corporation ("Dynamic on-die termination management", published October 17, 2006)
• US20040228196A1 to Kwak Jin-Seok ("Memory devices, systems and methods using selective on-die termination", published November 18, 2004)
• US6894691B2 to Dell Products L.P. ("Dynamic switching of parallel termination for power management with DDR memory", published May 17, 2005)

All these references were published before the priority date of US8947962 (December 21, 2006) and are therefore prior art.

Explanation of Obviousness

A person having ordinary skill in the art (POSITA) in memory system design would have been motivated to combine the teachings of US7123047B2, US20040228196A1, and US6894691B2 to arrive at the subject matter of Claim 1 of US8947962, for the following reasons:

1. Memory controller, connected to memory devices via an RQ bus, with ODT circuitry: US7123047B2 explicitly teaches a memory controller that performs "dynamic on-die termination management" on memory devices. This inherently presumes a memory system comprising a memory controller connected to memory devices, and that these memory devices include ODT circuitry. The use of an address and control (RQ) bus for communication between a memory controller and memory devices is a fundamental aspect of high-speed memory systems, commonly exemplified by DDR memory systems, as referenced in US6894691B2.

2. ODT circuitry connected to a subset of signal lines of the RQ bus: US20040228196A1 (Kwak) discloses memory systems and methods utilizing "selective on-die termination." Kwak specifically teaches that ODT can be applied to "selected data signals, or selected address signals, or selected command signals." This directly anticipates the concept of connecting ODT circuitry to only a "subset" of signal lines, including address and command signals, which constitute the RQ bus. A POSITA would readily understand how to apply this selective termination to the address and command signals of an RQ bus.

3. Memory controller operable to selectively disable the ODT circuitry in at least one memory device by driving control signals on a plurality of ODT control lines:

   • US7123047B2, titled "Dynamic on-die termination management," explicitly teaches the dynamic control of ODT, which encompasses the ability of a memory controller to selectively enable and disable ODT circuitry. This dynamic control is achieved by driving control signals.
   • US6894691B2 further reinforces this by disclosing "Dynamic switching of parallel termination for power management with DDR memory." Selectively disabling termination is a form of dynamic switching, and the motivation of "power management" is a key benefit highlighted in US8947962.
   • The concept of using "a plurality of ODT control lines" to manage ODT in a memory system is also well-established in the prior art. In multi-drop or multi-module memory architectures (such as those described in US6356106B1 for "Active termination in a multidrop memory system", or implicitly in US20050212551A1 for "efficient control of on-die termination"), individual control of ODT for different memory devices or modules is often required. This would naturally lead a POSITA to employ multiple control lines. Furthermore, even within a single memory device, multiple control signals might be used to select between different termination states (e.g., nominal, alternate, or disabled impedance values) as discussed in the background of US8947962 (e.g., CAODT and ALTCAODT pins).

Motivation for Combination

A POSITA would have been motivated to combine these teachings to achieve an optimized memory system. The core dynamic ODT management described in US7123047B2 provides flexibility in termination. Integrating the selective application of ODT to specific signal subsets (e.g., address and command lines) as taught by US20040228196A1 would allow for more granular control over signal integrity and reflections, tailoring termination to the specific characteristics and requirements of different signal types on the RQ bus. Finally, incorporating the power management benefits of dynamically disabling termination, as explicitly taught by US6894691B2, would lead to a more energy-efficient memory system, a desirable goal for any memory system designer. The claimed patent itself explicitly states that "dynamically controlling (enabling/disabling) the termination at the end of the RQ bus for a subset of signal provides a significant power saving advantage."

Therefore, it would have been obvious for a POSITA, motivated by optimizing signal integrity and reducing power consumption in memory systems, to combine the dynamic ODT management of US7123047B2 with the selective termination of signal subsets from US20040228196A1, including the ability to disable termination for power savings as disclosed in US6894691B2, using known control signal mechanisms.