Prior art

The USPTO provides a Patent Public Search tool that allows searching for patents and patent application publications. To search for a specific patent like 8907425, one would typically input the patent number into the search interface.

Based on the information provided, the following prior art is cited within US Patent 8907425:

Most Relevant Prior Art for US Patent 8907425:

1. U.S. Pat. No. 6,621,131 (U.S. Patent Publication No. 2003/0080361)
   • Full Citation: U.S. Pat. No. 6,621,131 (U.S. Patent Publication No. 2003/0080361)
   • Publication/Filing Date: While the publication date for US 6,621,131 is not explicitly stated in the provided text, the associated publication number US 2003/0080361 indicates a publication around 2003. The priority date for US8907425 is January 7, 2010.
   • Brief Description: This patent is cited as an example of methods for applying a compressive stress to the channel region in the gate length direction of p-type MIS transistors by forming a SiGe layer in a source/drain region. SiGe has a larger lattice constant than a silicon substrate, which induces the compressive stress.
   • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates aspects of Claims 1 and 16 of US8907425 that relate to forming a first source/drain region of a first conductivity type (p-type) including a silicon compound layer (SiGe) that causes a compressive stress in the channel region. The general concept of using SiGe in source/drain regions to induce compressive stress for enhanced p-type MIS transistor performance is disclosed.

Non-Patent Documents cited as prior art:

The patent also references two non-patent documents that disclose similar techniques:

1. T. Ghani et al., "A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors," IEDM Tech. Digest, pp. 978-980, 2003.

   • Publication Date: 2003
   • Brief Description: This document describes a 90 nm manufacturing logic technology that features strained silicon CMOS transistors. It is cited in the context of applying compressive stress to the channel region using SiGe in the source/drain region to enhance p-type MIS transistor performance.
   • Potential Anticipation (35 U.S.C. § 102): This non-patent literature potentially anticipates aspects of Claims 1 and 16 related to the use of silicon compound layers (strained silicon, by extension SiGe for compressive stress) in source/drain regions for applying stress to the channel region of MIS transistors.

2. Z. Luo et al., "Design of High Performance PFETs with Strained Si Channel and Laser Anneal," IEDM Tech. Digest, pp. 495-498, 2005.

   • Publication Date: 2005
   • Brief Description: This document discusses the design of high-performance PFETs (p-type Field-Effect Transistors) using strained silicon channels and laser annealing. It is also cited as an example of applying compressive stress to the channel region in the gate length direction by forming a SiGe layer in a source/drain region.
   • Potential Anticipation (35 U.S.C. § 102): Similar to the Ghani et al. paper, this document potentially anticipates aspects of Claims 1 and 16 concerning the fundamental technique of using silicon compound layers to induce stress in the channel region of p-type MIS transistors for performance enhancement.

These references primarily focus on the known technique of using SiGe layers in source/drain regions to induce compressive stress in the channel of p-type MIS transistors to improve drive capability. US Patent 8907425 differentiates itself by the specific structural arrangement that includes the uppermost surface of the silicon compound layer being higher than the substrate surface under the gate electrode, and the formation of a stress-relief film in the space between the silicon compound layer and the sidewall, which aims to mitigate adverse stress from the overlying stress insulating film.