Obviousness

The obviousness of US patent 8907425 under 35 U.S.C. § 103 can be assessed by examining whether a person having ordinary skill in the art (PHOSITA) would have been motivated to combine existing prior art to arrive at the claimed invention, particularly in light of the problem identified in the patent's background.

Independent Claims to be analyzed:

• Independent Claim 1 (Semiconductor Device Structure): This claim outlines a semiconductor device with a first Metal-Insulator-Semiconductor (MIS) transistor. Key features include a first source/drain region of a first conductivity type formed in a trench, which contains a silicon compound layer causing a "first stress" in the channel region. Crucially, the "uppermost surface of the silicon compound layer is located higher than a surface of the semiconductor substrate located directly under the first gate electrode." Furthermore, a "first stress-relief film is formed in a space between the silicon compound layer and the first sidewall." The device also includes a stress insulating film causing a "second stress" opposite to the first stress.
• Independent Claim 16 (Method for Fabricating a Semiconductor Device): This claim describes a fabrication method mirroring the structural features of Claim 1, including steps for forming the gate, sidewall, the silicon compound layer in a trench such that its uppermost surface is higher than the substrate surface under the gate, the first stress-relief film in the resulting space, and finally the stress insulating film.

Relevant Prior Art as identified in US8907425:

The "BACKGROUND" section of US8907425 explicitly describes the state of the art and the problem it aims to solve. It refers to:

1. Patent Document 1: U.S. Pat. No. 6,621,131 (U.S. Patent Publication No. 2003/0080361): Cited as an example of methods for applying compressive stress to a channel region by forming a SiGe layer in a source/drain region due to its larger lattice constant than a silicon substrate.
2. Conventional Semiconductor Devices (FIGS. 8A-10C of US8907425): The patent details a conventional fabrication process. This conventional device includes:
   • P-type MIS transistors (pMIS region) with source/drain regions formed from a SiGe layer (112) in trenches (111) to induce compressive stress (beneficial for p-type carriers).
   • N-type MIS transistors (nMIS region) with standard source/drain regions.
   • A global stress insulating film (118) formed over the entire surface, designed to induce tensile stress (beneficial for n-type carriers).

The Problem in the Prior Art:

US8907425 clearly articulates the problem with the conventional device: "In conventional semiconductor devices, it is possible to improve the drive capability of the n-type MIS transistor by using the stress insulating film 118 to apply a tensile stress to the channel region of the second active region 100b in the gate length direction. However, due to the stress insulating film 118, a tensile stress is applied to the channel region of the first active region 100a in the gate length direction. Thus, the drive capability of the p-type MIS transistor may be reduced." The objective of US8907425 is "to prevent a reduction in drive capability of a MIS transistor due to a stress insulating film, in a semiconductor device which includes a MIS transistor having a source/drain region including a silicon compound layer."

Obviousness Analysis and Motivation to Combine:

A PHOSITA (person having ordinary skill in the art) in the field of semiconductor device fabrication and stress engineering, confronted with the problem identified in the background of US8907425, would have been motivated to combine known techniques to arrive at the claimed invention.

The distinguishing features of Claim 1 (and the corresponding method of Claim 16) over the conventional device are primarily:

1. The silicon compound layer (e.g., SiGe layer 23) having an uppermost surface located higher than the surface of the semiconductor substrate directly under the first gate electrode (i.e., a "protruding portion").
2. A first stress-relief film (28a) formed in a space (24) between this protruding silicon compound layer and the first sidewall (19A).

Motivation for a PHOSITA to combine:

A PHOSITA would understand the following:

• Existing Knowledge from Prior Art: The conventional device (representing the general prior art including US6621131) already employs SiGe in pMOS source/drain regions to impart beneficial compressive stress to the channel. It also uses a global tensile stress insulating film to enhance nMOS performance, acknowledging that this film can adversely affect pMOS.
• Motivation for Enhancing Beneficial Stress: To further improve the drive capability of the p-type MIS transistor, a PHOSITA would be motivated to maximize the beneficial compressive stress from the SiGe layer. It is well-known in the art that forming "raised source/drain" structures, where the source/drain material protrudes above the original substrate surface, increases the volume of the strained material and thereby enhances the magnitude and effectiveness of the stress applied to the channel. Thus, modifying the SiGe layer to have a "protruding portion" (i.e., its uppermost surface located higher than the substrate surface under the gate) would be a straightforward and obvious design choice for a PHOSITA seeking to optimize pMOS performance.
• Motivation for Mitigating Undesirable Stress: The formation of a protruding SiGe layer naturally creates a physical "space" between the raised SiGe and the gate sidewall. Concurrently, the PHOSITA is aware that a global tensile stress insulating film (detrimental to pMOS) will be subsequently deposited. Faced with the explicit problem of this tensile film degrading pMOS performance, a PHOSITA would be motivated to reduce the undesirable stress transfer to the pMOS channel. A well-established engineering principle in semiconductor device design is to interpose buffer or isolation layers between stressed films and sensitive active regions to modulate or mitigate stress transmission. Therefore, filling this newly created space with a stress-relief dielectric material (such as silicon oxide, which is a common, relatively stress-neutral insulating film, as specifically disclosed for film 28a in US8907425) would be an obvious approach to buffer the pMOS channel from the detrimental tensile stress of the overlying stress insulating film.

Conclusion:

The claimed invention of US8907425 represents a combination of known elements and principles. A PHOSITA, motivated by the clearly articulated problem of conflicting stresses from the global stress insulating film in conventional CMOS technology, would have found it obvious to:

1. Enhance the beneficial compressive stress in pMOS by utilizing a raised SiGe source/drain structure (a known technique for increasing strain volume).
2. Recognize that this raised structure creates a space next to the gate sidewall.
3. Fill this space with a stress-relief dielectric material (a known method for stress buffering) to decouple the pMOS channel from the adverse effects of the global tensile stress insulating film.

The method claim (Claim 16) would also be rendered obvious, as the steps of forming a raised SiGe layer in a trench, and subsequently depositing and patterning insulating films to fill spaces and form stress-relief layers, are standard semiconductor fabrication techniques that a PHOSITA would employ to realize the obvious structural features. Therefore, the combination of the conventional device described in US8907425's background (informed by teachings like US6621131) with the general knowledge of raised source/drain structures and dielectric stress-buffering layers would have rendered the claimed invention obvious under 35 U.S.C. § 103.