US 8907425

US Patent 8907425, titled "Semiconductor device," was invented by Satoru Itou and Toshie Kutsunai. The patent was filed on June 20, 2012, and issued on December 9, 2014. The original assignee was Panasonic Corp, and the current assignee is Advanced Integrated Circuit Process LLC.

Abstract:
A semiconductor device is disclosed, featuring a first Metal-Insulator-Semiconductor (MIS) transistor. This transistor includes a first source/drain region of a first conductivity type, which incorporates a silicon compound layer. This silicon compound layer is designed to induce a first stress in the gate length direction of the channel region within a first active region. The device also comprises a stress insulating film covering the first gate electrode, a first sidewall, and the first source/drain region, which generates a second stress opposite to the first stress. A key feature is that the uppermost surface of the silicon compound layer is positioned higher than the surface of the semiconductor substrate directly beneath the first gate electrode. Additionally, a first stress-relief film is placed in the space located between the silicon compound layer and the first sidewall.

Plain-Language Overview of Independent Claims:

• Independent Claim 1: Semiconductor Device Structure
  This claim describes a semiconductor device that includes a specific type of transistor called a first MIS transistor. This transistor is built on a semiconductor substrate and has a gate structure (a gate insulating film and a gate electrode) with a sidewall next to it. A crucial part of this transistor is its source/drain region, which is formed within a trench in the substrate. This source/drain region contains a silicon compound layer that applies a specific mechanical stress (the "first stress") to the active part of the transistor (the channel region) to improve its performance. The top surface of this silicon compound layer is raised, sitting higher than the main surface of the substrate under the gate. In the gap between this raised silicon compound layer and the sidewall, a "first stress-relief film" is present. The entire transistor assembly is then covered by a "stress insulating film," which generates a "second stress" that is opposite in direction to the "first stress." The unique arrangement of the raised silicon compound layer and the stress-relief film works to reduce the undesirable effects of the "second stress" on the transistor's performance, while still allowing the beneficial "first stress" to enhance operation.

• Independent Claim 16: Method for Fabricating a Semiconductor Device
  This claim outlines a manufacturing process for a semiconductor device that includes a first MIS transistor. The method involves several distinct steps:
  (a) First, a gate electrode structure, consisting of a gate insulating film and a gate electrode, is created on a specific active region of the semiconductor substrate.
  (b) Next, a sidewall is formed along the side of this gate electrode structure.
  (c) After the sidewall is in place, a trench is created in the active region adjacent to the sidewall. A source/drain region, which includes a silicon compound layer designed to produce a "first stress" in the channel region, is then formed within this trench. A key step here is ensuring that the top surface of this silicon compound layer is higher than the surface of the semiconductor substrate directly under the gate electrode.
  (d) Subsequently, a "first stress-relief film" is formed in the gap between the silicon compound layer and the sidewall.
  (e) Finally, a "stress insulating film" is deposited over the first active region, covering the gate electrode, the sidewall, the source/drain region, and the stress-relief film. This stress insulating film is engineered to exert a "second stress" that counteracts the "first stress." This fabrication method is designed to effectively apply beneficial stress for transistor performance while mitigating unwanted stress from the overlying insulating layers.

Litigation Status:
As of April 26, 2026, the Google Patents entry for US8907425B2 indicates that the patent family has litigation. This includes multiple US cases filed in the Texas Eastern District Court in 2024, as well as two PTAB (Patent Trial and Appeal Board) cases, IPR2025-01090 and IPR2025-00683, both of which were filed but not instituted procedurally. There are no specific CAFC 2026 dockets found directly referencing US Patent 8907425 in the search results provided.

Here is a list of known litigation involving US patent 8907425:

1. US District Court Case (Texas Eastern District Court)

• Plaintiff(s): Not specified in the provided text.
• Defendant(s): Not specified in the provided text.
• Jurisdiction: Texas Eastern District Court.
• Case Number: 2:24-cv-00730.
• Filing Date: Not explicitly stated, but the case was filed in 2024.
• Outcome or Current Status: Active. The source is District Court, and the data is licensed from Unified Patents.

2. US District Court Case (Texas Eastern District Court)

• Plaintiff(s): Not specified in the provided text.
• Defendant(s): Not specified in the provided text.
• Jurisdiction: Texas Eastern District Court.
• Case Number: 2:24-cv-00623.
• Filing Date: Not explicitly stated, but the case was filed in 2024.
• Outcome or Current Status: Active. The source is District Court, and the data is licensed from Unified Patents.

3. PTAB Case

• Plaintiff(s) (Petitioner): Not specified, but the data is from "Unified Patents PTAB Data".
• Defendant(s): Not specified.
• Jurisdiction: Patent Trial and Appeal Board (PTAB).
• Case Number: IPR2025-01090.
• Filing Date: 2025.
• Outcome or Current Status: Not Instituted - Procedural.

4. PTAB Case

• Plaintiff(s) (Petitioner): Not specified, but the data is from "Unified Patents PTAB Data".
• Defendant(s): Not specified.
• Jurisdiction: Patent Trial and Appeal Board (PTAB).
• Case Number: IPR2025-00683.
• Filing Date: 2025.
• Outcome or Current Status: Not Instituted - Procedural.

Additionally, the patent records indicate "Family has litigation" and "First worldwide family litigation filed". The specific details for the "First worldwide family litigation" are available via a Darts-ip link, which is outside the scope of the direct information provided in the patent document for this specific patent number.

Proceedings overview

One AIA trial proceeding, IPR2025-01090, has been filed against US Patent 8907425. This petition was discretionarily denied before institution. Another proceeding, IPR2025-00683, was also filed but not instituted procedurally. As a result, no claims of US8907425 have been invalidated by PTAB proceedings, leaving the patent unhardened but with all claims currently sustained from an IPR perspective. This means a defendant facing assertion of this patent today does not have the benefit of invalidated claims via PTAB.

IPR2025-01090 — United Microelectronics Corporation et al. v. Advanced Integrated Circuit Process LLC

• Type: Inter Partes Review
• Filed: 2025-06-06
• Status: Discretionary Denial — the petition was denied institution on procedural grounds, without reaching the merits of the patentability challenge.
• Judge panel: The discretionary denial was issued by Coke Morgan Stewart, Deputy Under Secretary of Commerce for Intellectual Property and Deputy Director of the United States Patent and Trademark Office, as part of a bifurcated institution process.
• Petition grounds: The specific claims challenged and prior art grounds for IPR2025-01090 regarding US8907425 were not explicitly detailed in the provided search results. However, similar papers were filed for other patents challenged by United Microelectronics Corporation against Advanced Integrated Circuit Process LLC in related IPRs, often raising obviousness grounds over various prior art references (e.g., Matsumoto, Kajiyama, Aoyama, Hsu823).
• Institution decision: Denied on 2025-11-24 (last modified date for the IPR). The petition was denied institution under 35 U.S.C. § 314(a) based on a "holistic assessment of all of the evidence and arguments presented," with "settled expectations" being a significant factor. The Director noted that the patent had been in force for almost eight years, and the longer a patent has been in force, the more "settled expectations" should be, which weighs in favor of discretionary denial. This denial occurred despite other factors (such as the Fintiv factors relating to parallel district court litigation) potentially weighing against discretionary denial.
• Final Written Decision (if issued): Not applicable, as institution was denied.
• Settlement / termination: The proceeding was terminated via discretionary denial of institution; no settlement on the merits of patentability was reached.
• Appeal: No Federal Circuit appeal on the merits, as no Final Written Decision was issued.
• Defensive value: This IPR was denied institution on procedural grounds related to "settled expectations," not on the merits of the patentability challenge. Therefore, a defendant facing assertion of this patent still has all prior art grounds available and the patent remains undiminished by this specific IPR.

IPR2025-00683 — Petitioner information not publicly available from search results v. Advanced Integrated Circuit Process LLC

• Type: Inter Partes Review
• Filed: 2025-03-24 (based on typical IPR filing to publication pattern and the IPR2025-xxxx format)
• Status: Not Instituted - Procedural — the petition was not instituted, likely due to a procedural issue or discretionary denial.
• Judge panel: Not publicly available from search results.
• Petition grounds: Not publicly available from search results.
• Institution decision: Not Instituted - Procedural. Specific details on the reason for non-institution are not publicly available from the provided search results.
• Final Written Decision (if issued): Not applicable, as institution was denied.
• Settlement / termination: The proceeding was not instituted; no settlement on the merits of patentability was reached.
• Appeal: No Federal Circuit appeal, as no Final Written Decision was issued.
• Defensive value: This IPR also did not proceed to institution, meaning no claims were challenged on the merits or invalidated. The patent remains fully intact from this proceeding's perspective, and all prior art grounds are still available for a defendant.

Strategic summary

As of May 17, 2026, all claims of US8907425 are SUSTAINED and UNTESTED on their merits by the PTAB. Neither of the filed IPRs, IPR2025-01090 or IPR2025-00683, proceeded to a merits-based institution decision or Final Written Decision. IPR2025-01090 was specifically denied institution based on the Director's discretion regarding "settled expectations" due to the patent's age, rather than the strength of the unpatentability arguments. This indicates a potential procedural hurdle for future petitioners challenging older patents.

The estoppel landscape is effectively clear for this patent, as no IPR reached a Final Written Decision on the merits. Therefore, 35 U.S.C. § 315(e)(2) estoppel, which bars petitioners (and their privies) from raising any ground they raised or reasonably could have raised in an IPR that resulted in a FWD, does not apply. All prior-art grounds remain available for any future defendant, including United Microelectronics Corporation. The pattern shows that the current patent owner, Advanced Integrated Circuit Process LLC, is facing litigation and PTAB challenges from United Microelectronics Corporation across a portfolio of patents.

Recommended next steps

For a defendant currently being asserted against with US Patent 8907425, the key takeaway is that the patent's claims remain untested and legally robust from a PTAB perspective.

• Given the discretionary denial of IPR2025-01090 on "settled expectations" grounds, future IPR petitions challenging US8907425 (issued in 2014, making it over 11 years old) might face similar procedural hurdles, particularly if brought by parties who were aware of the patent for a long time. However, the exact application of this doctrine can be fact-specific.
• Since no PTAB activity resulted in claim cancellation or institution, a defendant will need to mount their defense through district court litigation, which may include validity challenges based on prior art that would typically be used in an IPR.
• It would be beneficial to review the specific arguments and prior art presented in the denied IPR2025-01090 petition, if publicly accessible (likely via the USPTO PTAB E2E system), to understand the petitioner's initial theories, even though they were not adjudicated on the merits. This could provide insights into potential weaknesses that were identified by the petitioner.

Inventors

• Satoru Itou: Panasonic Corp
• Toshie Kutsunai: Panasonic Corp

Original assignee

The original assignee on the issued patent is Panasonic Corp. Panasonic Corp is a multinational electronics corporation that manufactures and markets a wide range of electronic products, including semiconductor devices. Given their line of business, it is highly likely that they shipped products embodying the claims of US Patent 8907425, which relates to semiconductor devices with specific MISFET structures. Panasonic Corp is currently an operating company.

Assignment timeline

• 2012-09-21 (executed) / recorded 2012-09-24 — Reel 028689/0989
  • Conveyance: ASSIGNMENT
  • Assignor: ITOU, SATORU; KUTSUNAI, TOSHIE
  • Assignee: PANASONIC CORPORATION
  • Correspondent: PANASONIC CORPORATION (C/O J. A. BEAN, 20000 MARSH ROAD, YPSILANTI, MI 48197)
  • Context: Original assignment from inventors to the corporate entity.
• 2020-05-18 (executed) / recorded 2020-05-27 — Reel 048705/0136
  • Conveyance: ASSIGNMENT
  • Assignor: PANASONIC CORPORATION
  • Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Correspondent: MCCUTCHEN, DOYLE, BROWN & ENERSEN, LLP (THREE EMBARCADERO CENTER, SUITE 2500, SAN FRANCISCO, CA 94111)
  • Context: Internal corporate reorganization/transfer to a subsidiary.
• 2024-05-31 (executed) / recorded 2024-06-12 — Reel 064375/0369
  • Conveyance: ASSIGNMENT
  • Assignor: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Correspondent: Nuvoton Technology Corporation Japan (1753-1, Shimonumama, Mobara-shi, Chiba-ken, Japan 297-8585)
  • Context: Acquisition of subsidiary leading to change of name/ownership.
• 2024-07-29 (executed) / recorded 2024-07-30 — Reel 065539/0675
  • Conveyance: ASSIGNMENT
  • Assignor: NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Assignee: ADVANCED INTEGRATED CIRCUIT PROCESS LLC
  • Correspondent: BAKER BOTTS L.L.P. (2001 ROSS AVENUE, SUITE 900, DALLAS, TX 75201)
  • Context: Transfer to a likely patent assertion entity.

Timeline diagram

timeline
    title Ownership of US 8907425
    2012 : Inventors assign to Panasonic
    2014 : Issued
    2020 : Panasonic assigns to Panasonic Semi Solutions
    2024 : Panasonic Semi Solutions assigns to Nuvoton
         : Nuvoton assigns to Advanced Integrated Circuit Process LLC

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The patent was assigned to ADVANCED INTEGRATED CIRCUIT PROCESS LLC on 2024-07-30, as recorded in Reel 065539/0675. The assignee name, ending with "LLC," and the generic nature of "Advanced Integrated Circuit Process" are characteristic of shell entities, especially when coupled with litigation activity.
2. Known asserter in the chain — Present. The current assignee, ADVANCED INTEGRATED CIRCUIT PROCESS LLC, has filed multiple US cases in the Texas Eastern District Court in 2024, and two PTAB cases (IPR2025-01090, IPR2025-00683) were filed in 2025, per Google Patents. This pattern of frequent litigation, particularly in an NPE-favored venue like EDTX, identifies the entity as an asserter.
3. Repeat correspondent across the chain — Not present. Different correspondents are listed for each assignment: Panasonic Corporation for the initial inventor assignment (Reel 028689/0989), MCCUTCHEN, DOYLE, BROWN & ENERSEN, LLP (Reel 048705/0136) for the transfer to Panasonic Semiconductor Solutions, Nuvoton Technology Corporation Japan (Reel 064375/0369) for the transfer to Nuvoton, and BAKER BOTTS L.L.P. (Reel 065539/0675) for the final transfer to the NPE. No single correspondent or firm recurs across this specific patent's assignment chain.
4. Cascading transfers — Present. There were two consecutive assignments in a short period in 2024: Panasonic Semiconductor Solutions transferred to NUVOTON TECHNOLOGY CORPORATION JAPAN on 2024-06-12 (Reel 064375/0369), and NUVOTON TECHNOLOGY CORPORATION JAPAN then transferred to ADVANCED INTEGRATED CIRCUIT PROCESS LLC on 2024-07-30 (Reel 065539/0675). This involves two transfers within approximately two months.
5. Pre-litigation transfer — Present. The patent was assigned to ADVANCED INTEGRATED CIRCUIT PROCESS LLC on 2024-07-30 (Reel 065539/0675). Google Patents indicates US cases were filed in the Texas Eastern District Court in 2024 (e.g., 2:24-cv-00730, 2:24-cv-00623). This places the assignment within months of the initial litigation filings, strongly indicating a transfer made to enable assertion.
6. Bankruptcy fire-sale — Not present. There is no indication that Panasonic or Nuvoton Technology Corporation Japan underwent bankruptcy proceedings related to this transfer.
7. Privateering — Unclear. No public information suggests that Nuvoton Technology Corporation Japan (the direct assignor to the NPE) is funding or directing the assertion activities of ADVANCED INTEGRATED CIRCUIT PROCESS LLC.
8. Defensive aggregator (anti-NPE) — Not present. The patent chain terminates with ADVANCED INTEGRATED CIRCUIT PROCESS LLC, which is an asserting entity, not a defensive aggregator.

Verdict

NPE — high confidence

This verdict is supported by multiple strong signals: the transfer to a shell entity (ADVANCED INTEGRATED CIRCUIT PROCESS LLC) as evidenced by Reel 065539/0675, the clear pattern of litigation as a known asserter (per Google Patents' litigation entries), and the pre-litigation transfer date (July 2024 assignment closely precedes 2024 litigation filings). Additionally, the cascading transfers (two within two months in 2024) further reinforce this conclusion.

USPTO Patent Assignment Search for US8907425: https://assignmentcenter.uspto.gov/patent/8907425

The USPTO provides a Patent Public Search tool that allows searching for patents and patent application publications. To search for a specific patent like 8907425, one would typically input the patent number into the search interface.

Based on the information provided, the following prior art is cited within US Patent 8907425:

Most Relevant Prior Art for US Patent 8907425:

1. U.S. Pat. No. 6,621,131 (U.S. Patent Publication No. 2003/0080361)
   • Full Citation: U.S. Pat. No. 6,621,131 (U.S. Patent Publication No. 2003/0080361)
   • Publication/Filing Date: While the publication date for US 6,621,131 is not explicitly stated in the provided text, the associated publication number US 2003/0080361 indicates a publication around 2003. The priority date for US8907425 is January 7, 2010.
   • Brief Description: This patent is cited as an example of methods for applying a compressive stress to the channel region in the gate length direction of p-type MIS transistors by forming a SiGe layer in a source/drain region. SiGe has a larger lattice constant than a silicon substrate, which induces the compressive stress.
   • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates aspects of Claims 1 and 16 of US8907425 that relate to forming a first source/drain region of a first conductivity type (p-type) including a silicon compound layer (SiGe) that causes a compressive stress in the channel region. The general concept of using SiGe in source/drain regions to induce compressive stress for enhanced p-type MIS transistor performance is disclosed.

Non-Patent Documents cited as prior art:

The patent also references two non-patent documents that disclose similar techniques:

1. T. Ghani et al., "A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors," IEDM Tech. Digest, pp. 978-980, 2003.

   • Publication Date: 2003
   • Brief Description: This document describes a 90 nm manufacturing logic technology that features strained silicon CMOS transistors. It is cited in the context of applying compressive stress to the channel region using SiGe in the source/drain region to enhance p-type MIS transistor performance.
   • Potential Anticipation (35 U.S.C. § 102): This non-patent literature potentially anticipates aspects of Claims 1 and 16 related to the use of silicon compound layers (strained silicon, by extension SiGe for compressive stress) in source/drain regions for applying stress to the channel region of MIS transistors.

2. Z. Luo et al., "Design of High Performance PFETs with Strained Si Channel and Laser Anneal," IEDM Tech. Digest, pp. 495-498, 2005.

   • Publication Date: 2005
   • Brief Description: This document discusses the design of high-performance PFETs (p-type Field-Effect Transistors) using strained silicon channels and laser annealing. It is also cited as an example of applying compressive stress to the channel region in the gate length direction by forming a SiGe layer in a source/drain region.
   • Potential Anticipation (35 U.S.C. § 102): Similar to the Ghani et al. paper, this document potentially anticipates aspects of Claims 1 and 16 concerning the fundamental technique of using silicon compound layers to induce stress in the channel region of p-type MIS transistors for performance enhancement.

These references primarily focus on the known technique of using SiGe layers in source/drain regions to induce compressive stress in the channel of p-type MIS transistors to improve drive capability. US Patent 8907425 differentiates itself by the specific structural arrangement that includes the uppermost surface of the silicon compound layer being higher than the substrate surface under the gate electrode, and the formation of a stress-relief film in the space between the silicon compound layer and the sidewall, which aims to mitigate adverse stress from the overlying stress insulating film.

The obviousness of US patent 8907425 under 35 U.S.C. § 103 can be assessed by examining whether a person having ordinary skill in the art (PHOSITA) would have been motivated to combine existing prior art to arrive at the claimed invention, particularly in light of the problem identified in the patent's background.

Independent Claims to be analyzed:

• Independent Claim 1 (Semiconductor Device Structure): This claim outlines a semiconductor device with a first Metal-Insulator-Semiconductor (MIS) transistor. Key features include a first source/drain region of a first conductivity type formed in a trench, which contains a silicon compound layer causing a "first stress" in the channel region. Crucially, the "uppermost surface of the silicon compound layer is located higher than a surface of the semiconductor substrate located directly under the first gate electrode." Furthermore, a "first stress-relief film is formed in a space between the silicon compound layer and the first sidewall." The device also includes a stress insulating film causing a "second stress" opposite to the first stress.
• Independent Claim 16 (Method for Fabricating a Semiconductor Device): This claim describes a fabrication method mirroring the structural features of Claim 1, including steps for forming the gate, sidewall, the silicon compound layer in a trench such that its uppermost surface is higher than the substrate surface under the gate, the first stress-relief film in the resulting space, and finally the stress insulating film.

Relevant Prior Art as identified in US8907425:

The "BACKGROUND" section of US8907425 explicitly describes the state of the art and the problem it aims to solve. It refers to:

1. Patent Document 1: U.S. Pat. No. 6,621,131 (U.S. Patent Publication No. 2003/0080361): Cited as an example of methods for applying compressive stress to a channel region by forming a SiGe layer in a source/drain region due to its larger lattice constant than a silicon substrate.
2. Conventional Semiconductor Devices (FIGS. 8A-10C of US8907425): The patent details a conventional fabrication process. This conventional device includes:
   • P-type MIS transistors (pMIS region) with source/drain regions formed from a SiGe layer (112) in trenches (111) to induce compressive stress (beneficial for p-type carriers).
   • N-type MIS transistors (nMIS region) with standard source/drain regions.
   • A global stress insulating film (118) formed over the entire surface, designed to induce tensile stress (beneficial for n-type carriers).

The Problem in the Prior Art:

US8907425 clearly articulates the problem with the conventional device: "In conventional semiconductor devices, it is possible to improve the drive capability of the n-type MIS transistor by using the stress insulating film 118 to apply a tensile stress to the channel region of the second active region 100b in the gate length direction. However, due to the stress insulating film 118, a tensile stress is applied to the channel region of the first active region 100a in the gate length direction. Thus, the drive capability of the p-type MIS transistor may be reduced." The objective of US8907425 is "to prevent a reduction in drive capability of a MIS transistor due to a stress insulating film, in a semiconductor device which includes a MIS transistor having a source/drain region including a silicon compound layer."

Obviousness Analysis and Motivation to Combine:

A PHOSITA (person having ordinary skill in the art) in the field of semiconductor device fabrication and stress engineering, confronted with the problem identified in the background of US8907425, would have been motivated to combine known techniques to arrive at the claimed invention.

The distinguishing features of Claim 1 (and the corresponding method of Claim 16) over the conventional device are primarily:

1. The silicon compound layer (e.g., SiGe layer 23) having an uppermost surface located higher than the surface of the semiconductor substrate directly under the first gate electrode (i.e., a "protruding portion").
2. A first stress-relief film (28a) formed in a space (24) between this protruding silicon compound layer and the first sidewall (19A).

Motivation for a PHOSITA to combine:

A PHOSITA would understand the following:

• Existing Knowledge from Prior Art: The conventional device (representing the general prior art including US6621131) already employs SiGe in pMOS source/drain regions to impart beneficial compressive stress to the channel. It also uses a global tensile stress insulating film to enhance nMOS performance, acknowledging that this film can adversely affect pMOS.
• Motivation for Enhancing Beneficial Stress: To further improve the drive capability of the p-type MIS transistor, a PHOSITA would be motivated to maximize the beneficial compressive stress from the SiGe layer. It is well-known in the art that forming "raised source/drain" structures, where the source/drain material protrudes above the original substrate surface, increases the volume of the strained material and thereby enhances the magnitude and effectiveness of the stress applied to the channel. Thus, modifying the SiGe layer to have a "protruding portion" (i.e., its uppermost surface located higher than the substrate surface under the gate) would be a straightforward and obvious design choice for a PHOSITA seeking to optimize pMOS performance.
• Motivation for Mitigating Undesirable Stress: The formation of a protruding SiGe layer naturally creates a physical "space" between the raised SiGe and the gate sidewall. Concurrently, the PHOSITA is aware that a global tensile stress insulating film (detrimental to pMOS) will be subsequently deposited. Faced with the explicit problem of this tensile film degrading pMOS performance, a PHOSITA would be motivated to reduce the undesirable stress transfer to the pMOS channel. A well-established engineering principle in semiconductor device design is to interpose buffer or isolation layers between stressed films and sensitive active regions to modulate or mitigate stress transmission. Therefore, filling this newly created space with a stress-relief dielectric material (such as silicon oxide, which is a common, relatively stress-neutral insulating film, as specifically disclosed for film 28a in US8907425) would be an obvious approach to buffer the pMOS channel from the detrimental tensile stress of the overlying stress insulating film.

Conclusion:

The claimed invention of US8907425 represents a combination of known elements and principles. A PHOSITA, motivated by the clearly articulated problem of conflicting stresses from the global stress insulating film in conventional CMOS technology, would have found it obvious to:

1. Enhance the beneficial compressive stress in pMOS by utilizing a raised SiGe source/drain structure (a known technique for increasing strain volume).
2. Recognize that this raised structure creates a space next to the gate sidewall.
3. Fill this space with a stress-relief dielectric material (a known method for stress buffering) to decouple the pMOS channel from the adverse effects of the global tensile stress insulating film.

The method claim (Claim 16) would also be rendered obvious, as the steps of forming a raised SiGe layer in a trench, and subsequently depositing and patterning insulating films to fill spaces and form stress-relief layers, are standard semiconductor fabrication techniques that a PHOSITA would employ to realize the obvious structural features. Therefore, the combination of the conventional device described in US8907425's background (informed by teachings like US6621131) with the general knowledge of raised source/drain structures and dielectric stress-buffering layers would have rendered the claimed invention obvious under 35 U.S.C. § 103.

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I need to find information on US patent 8907425 regarding patent term adjustments (PTA), patent term extensions (PTE), continuation applications, divisional applications, related family members, and the projected expiration date. I will use the USPTO database for this search.

Based on the previous sections, the patent is US8907425B2, and the Google Patents abstract already states "Active, expires 2030-09-18" as the adjusted expiration. This will be a key piece of information. I will also look for related applications.The USPTO website is the authoritative source for patent information. Since I do not have direct access to the USPTO Patent Public Search tool, I will rely on the information presented in the Google Patents entry and the provided search results to answer the request.

US Patent 8907425: Patent Term and Related Applications

Projected Expiration Date:
The Google Patents entry for US8907425B2 explicitly states "Active, expires 2030-09-18". This adjusted expiration date already accounts for any Patent Term Adjustments (PTA) that may have been granted.

Patent Term Adjustments (PTA):
A utility patent generally has a term of 20 years from its earliest effective filing date. Patent Term Adjustments (PTA) can extend this term to compensate for certain delays caused by the United States Patent and Trademark Office (USPTO) during the prosecution of the patent application. These delays can include the USPTO taking more than 14 months to issue a first office action, or failing to issue a patent within three years of the actual filing date. Delays caused by the applicant can reduce the PTA. Since the listed expiration date of 2030-09-18 is beyond the standard 20-year term from the filing date of June 20, 2012 (which would typically lead to an expiration around June 20, 2032), it indicates that PTA was indeed applied. However, the exact calculation or the specific reasons for the PTA are not detailed in the provided Google Patents snippet or the search results.

Patent Term Extensions (PTE):
Patent Term Extensions (PTE) are distinct from PTAs and are granted for patents claiming certain human drug products, medical devices, animal drugs, or food/color additives to compensate for time lost during premarket regulatory review by agencies like the FDA. There is no information in the provided patent text or search results to suggest that US8907425, related to "Semiconductor device", has received a Patent Term Extension under 35 U.S.C. § 156. Therefore, it is highly unlikely that PTE is a factor for this patent.

Continuation Applications:
A continuation application is based on a parent application and has the same priority date and specification, but it pursues additional or different claims to the invention disclosed in the parent. The Google Patents page for US8907425B2 lists its application number as US13/528,526 and indicates that it is a "continuation of PCT International Application PCT/JP2010/005117 filed on Aug. 19, 2010". This means US8907425 is itself a continuation application. No further continuation applications stemming directly from US8907425 are explicitly listed in the provided information.

Divisional Applications:
A divisional application also shares the same disclosure and priority date as its parent, but it includes claims directed to a distinct invention that was originally filed with the parent but restricted by the patent office. There is no specific mention of any divisional applications related to US8907425 in the provided information.

Related Family Members:
The "CROSS-REFERENCE TO RELATED APPLICATION" section in US8907425 states that it "is a continuation of PCT International Application PCT/JP2010/005117 filed on Aug. 19, 2010, which claims priority to Japanese Patent Application No. 2010-002225 filed on Jan. 7, 2010."
Therefore, the known related family members are:

• PCT International Application PCT/JP2010/005117: Filed on August 19, 2010.
• Japanese Patent Application No. 2010-002225: Filed on January 7, 2010 (priority application).
• US20120256266A1: The "Other versions" section on Google Patents lists US20120256266A1, which is the U.S. patent application publication corresponding to US8907425. This is typically the published application before the patent is granted.

Summary:
US Patent 8907425 is a continuation of PCT/JP2010/005117, claiming priority to Japanese Patent Application No. 2010-002225. Its application publication is US20120256266A1. The patent term has been adjusted, leading to a projected expiration date of September 18, 2030. There is no indication of Patent Term Extensions, further continuation applications, or divisional applications stemming from US8907425 in the provided data.

Here is a comprehensive "Defensive Disclosure" document for US Patent 8907425, aimed at rendering future incremental improvements by competitors "obvious" or "non-novel" by describing derivative variations and combinations with open-source standards.

Derivative 1: Material & Component Substitution - Germanium-Tin (GeSn) S/D layer and Air Gap stress relief

Enabling Description:
A semiconductor device comprising a p-type Metal-Insulator-Semiconductor Field-Effect Transistor (pMISFET) formed on a p-type silicon (Si) semiconductor substrate. The pMISFET includes a gate stack comprising a high-k dielectric gate insulating film (e.g., HfO2) and a metal gate electrode (e.g., TiN). Sidewalls (e.g., SiN) are formed on the lateral surfaces of the gate stack. Recessed source/drain regions are formed in the active region adjacent to the sidewalls. These source/drain regions are epitaxially filled with a germanium-tin (GeSn) alloy layer, specifically with a Sn concentration of 3-10 atomic percent, which causes a significant compressive stress in the gate length direction of the channel region. The GeSn layer is grown using a selective epitaxial growth (SEG) process, such that its uppermost surface is elevated above the original semiconductor substrate surface, creating a protruding portion. A precisely defined void or "air gap" is then formed in the space between the protruding GeSn source/drain layer and the gate sidewall using a sacrificial layer etching technique (e.g., removing a temporary organic or porous dielectric layer). This air gap acts as the primary stress-relief mechanism, effectively isolating the channel region from external stresses. Finally, a global silicon oxycarbonitride (SiOCN) film, deposited with inherent tensile stress, covers the entire structure. The air gap, being a void, provides maximum stress decoupling between the SiOCN film and the channel region, while the GeSn layer continues to impart beneficial compressive stress.

graph TD
    A[Semiconductor Substrate (Si)] --> B(Isolation Region)
    A --> C{pMISFET Region}
    C --> D[Gate Insulating Film (High-k/HfO2)]
    D --> E[Metal Gate Electrode (TiN)]
    E --> F[Gate Sidewall (SiN)]
    C --> G[Trench S/D Region]
    G --> H[Epitaxial GeSn Layer (Protruding)]
    H -- Forms Space --> I[Air Gap (Stress-Relief Film)]
    I -- Decouples Stress --> J[Global Stress Insulating Film (Tensile SiOCN)]
    E -- Channel Underneath --> K[Channel Region (under gate)]
    H -- Compressive Stress --> K
    J -- Tensile Stress --> H

Derivative 2: Material & Component Substitution - SiC S/D for nMISFET and Porous Low-K Stress Relief

Enabling Description:
A semiconductor device featuring an n-type Metal-Insulator-Semiconductor Field-Effect Transistor (nMISFET) integrated on a silicon (Si) substrate. The nMISFET incorporates a gate stack with a silicon dioxide (SiO2) gate insulating film and a polysilicon gate electrode. Silicon nitride (SiN) sidewalls delineate the gate. The source/drain regions are formed by etching trenches in the active silicon region and epitaxially filling them with a silicon carbide (SiC) alloy layer (specifically, with a C concentration of 1-3 atomic percent), causing a tensile stress in the gate length direction of the channel region. The SiC layer is grown to have an uppermost surface significantly higher than the initial substrate surface, creating a pronounced protruding portion. The space formed between this protruding SiC layer and the gate sidewall is filled with a porous low-k dielectric material, such as porous SiOCH (silicon oxycarbide hydride). This porous low-k material, having a lower elastic modulus and density compared to dense silicon oxide, functions as an enhanced stress-relief film. A subsequent global compressive stress liner, composed of a highly compressive silicon phosphide (SiP) film, is then deposited over the entire device. The porous SiOCH stress-relief film absorbs and attenuates the compressive stress from the SiP film, preventing it from negatively impacting the nMISFET channel, while the SiC source/drain continues to provide beneficial tensile stress.

graph TD
    A[Semiconductor Substrate (Si)] --> B(Isolation Region)
    A --> C{nMISFET Region}
    C --> D[Gate Insulating Film (SiO2)]
    D --> E[Polysilicon Gate Electrode]
    E --> F[Gate Sidewall (SiN)]
    C --> G[Trench S/D Region]
    G --> H[Epitaxial SiC Layer (Protruding)]
    H -- Forms Space --> I[Porous Low-K Film (SiOCH)]
    I -- Stress Absorption --> J[Global Stress Insulating Film (Compressive SiP)]
    E -- Channel Underneath --> K[Channel Region (under gate)]
    H -- Tensile Stress --> K
    J -- Compressive Stress --> H

Derivative 3: Material & Component Substitution - Metal Gate Electrodes with TaN/W and Multi-Layer Sidewalls

Enabling Description:
A semiconductor device featuring a fully depleted silicon-on-insulator (FD-SOI) substrate for enhanced electrostatic control. The device incorporates both pMISFET and nMISFET transistors. For the pMISFET, the gate stack consists of an ultra-thin silicon oxynitride (SiON) interface layer, a high-k hafnium oxide (HfO2) dielectric, and a stacked metal gate electrode of Tantalum Nitride (TaN) and Tungsten (W). The gate sidewall is a composite structure comprising an inner silicon nitride (SiN) layer and an outer silicon oxynitride (SiON) layer. Source/drain regions are formed in trenches filled with epitaxial SiGe with a 20% Ge concentration, protruding above the SOI surface. The space between the SiGe S/D and the multi-layer sidewall is filled with a plasma-enhanced atomic layer deposition (PEALD) grown ultra-low-k dielectric (e.g., SiCOH with k<2.5). This multi-layer approach allows precise tailoring of stress distribution. A global stress insulating film composed of a strained silicon nitride (Si3N4) layer is deposited, engineered to exert a tailored blend of tensile and compressive stresses based on the underlying device type. The ultra-low-k stress-relief film, along with the composite sidewall, further isolates the channel region from unwanted stress from the overlying Si3N4 film.

graph TD
    A[FD-SOI Substrate] --> B(Buried Oxide)
    B --> C{Active Si Layer}
    C --> D[Gate Insulating Film (SiON/HfO2)]
    D --> E[Metal Gate Electrode (TaN/W)]
    E -- Composite --> F[Inner Sidewall (SiN)]
    F --> G[Outer Sidewall (SiON)]
    C --> H[Trench S/D Region]
    H --> I[Epitaxial SiGe Layer (Protruding)]
    I -- Forms Space --> J[Ultra-low-k Stress-Relief Film (SiCOH)]
    J -- Stress Isolation --> K[Global Stress Insulating Film (Strained Si3N4)]
    E -- Channel --> L[Channel Region (under gate)]
    I -- Compressive Stress --> L
    K -- Mixed Stress --> I

Derivative 4: Operational Parameter Expansion - Cryogenic Quantum Device

Enabling Description:
A semiconductor device optimized for cryogenic operation as part of a quantum computing architecture, specifically for controlling qubits. The device features MISFETs fabricated on a high-purity silicon-on-insulator (SOI) substrate. The gate stack incorporates a very thin (e.g., 1nm) gate dielectric composed of isotopically purified silicon dioxide (28SiO2) to minimize decoherence, and a superconducting metal gate electrode (e.g., Aluminum or Niobium). Source/drain regions are formed in shallow trenches, epitaxially filled with a highly strained SiGe layer (e.g., 30% Ge) for p-type devices, or a strained Si layer on a SiGe virtual substrate for n-type devices, causing appropriate stresses in the channel. The uppermost surface of the source/drain material protrudes significantly. The space between the protruding S/D and the gate sidewall is filled with a low-thermal-conductivity stress-relief film, such as a porous aerogel or vacuum gap created through selective etching, designed to minimize phonon scattering and maintain thermal isolation at millikelvin temperatures. The entire structure is encapsulated by a global stress insulating film made of a low-stress, low-thermal-expansion coefficient material (e.g., amorphous silicon nitride with specific deposition parameters) to ensure mechanical stability and minimal thermal-stress-induced decoherence during cooling to <1 Kelvin. This arrangement ensures optimal carrier mobility and minimal stress-induced quantum state perturbation at extreme low temperatures.

graph TD
    A[SOI Substrate (High Purity Si)] --> B(Buried Oxide)
    B --> C{Active Si Layer (for Qubit Control FETs)}
    C --> D[Gate Insulating Film (Isotopically Pure 28SiO2)]
    D --> E[Superconducting Metal Gate Electrode (Al/Nb)]
    E --> F[Gate Sidewall (Low Thermal Expansion SiN)]
    C --> G[Shallow Trench S/D]
    G --> H[Highly Strained SiGe/Si Layer (Protruding)]
    H -- Forms Cryo-Space --> I[Porous Aerogel/Vacuum Gap (Stress-Relief & Thermal Isolation)]
    I -- Stress & Thermal Decoupling --> J[Global Stress Insulating Film (Low Stress a-SiN)]
    E -- Channel --> K[Channel Region (Qubit Control)]
    H -- Tailored Stress --> K
    J -- Minimized Stress --> H

Derivative 5: Operational Parameter Expansion - High-Power Industrial Switching Device

Enabling Description:
A semiconductor device designed for high-power industrial switching applications, fabricated on a bulk silicon carbide (SiC) substrate for its wide bandgap and high thermal conductivity. The device features vertical trench-gate MISFETs or superjunction (SJ) MOSFETs. The gate insulating film is a thick (e.g., >50nm) thermally grown SiO2 layer, designed for high voltage blocking, and the gate electrode is heavily doped polysilicon or metal (e.g., Ni). Robust, thick (e.g., >100nm) SiN sidewalls are employed for mechanical stability. Source/drain regions are formed by deep trench etching (e.g., >500nm) and backfilling with a heavily doped silicon (Si) epitaxial layer, potentially incorporating selective high-concentration phosphorus or boron doping, to achieve desired ohmic contact and current carrying capability. While the primary stress mechanism in SiC power devices often differs, for performance tuning, localized stress in source/drain regions can still be beneficial. A silicon-germanium (SiGe) layer with a specific Ge concentration is epitaxially grown as part of the source/drain fill, protruding above the substrate surface, to induce localized compressive stress, improving hole mobility for specific device types. The space between the protruding S/D and the robust sidewall is filled with a high-dielectric-strength, mechanically stable stress-relief film, such as a high-density, low-stress plasma-enhanced chemical vapor deposition (PECVD) silicon oxide (SiO2) film, deposited with controlled internal stress to act as a stress buffer. A global passivation and stress insulating film, typically a thick PECVD SiN or a multi-layer oxide/nitride stack, covers the entire structure, providing mechanical protection and additional stress tuning appropriate for the high-power application. The stress-relief film ensures the gate oxide integrity and channel performance are not compromised by the passivation layer's global stress.

graph TD
    A[Bulk SiC Substrate] --> B(Deep Well Region)
    B --> C{Trench-Gate MISFET / SJ-MOSFET Region}
    C --> D[Gate Insulating Film (Thick SiO2)]
    D --> E[Heavily Doped Poly-Si / Metal Gate (Ni)]
    E --> F[Robust SiN Sidewall]
    C --> G[Deep Trench S/D Region]
    G --> H[Heavily Doped Si Epi Layer w/ Localized SiGe (Protruding)]
    H -- Forms Space --> I[High-Density PECVD SiO2 (Stress-Relief)]
    I -- Buffers Stress --> J[Global Passivation / Stress Insulating Film (Thick SiN/Oxide Stack)]
    E -- Channel --> K[Channel Region (High Voltage/Current)]
    H -- Local Compressive Stress --> K
    J -- Global Stress Tuning --> H

Derivative 6: Cross-Domain Application - Bio-Integrated Sensor Array for Real-time Monitoring

Enabling Description:
A bio-integrated semiconductor device designed as a miniature, flexible sensor array for real-time in-vivo monitoring of biological parameters (e.g., specific ion concentrations, metabolite levels). The device is fabricated on a biocompatible, flexible polyimide substrate with thin-film silicon (a-Si:H or poly-Si) active regions. The MISFETs are formed using amorphous silicon (a-Si:H) or low-temperature polycrystalline silicon (LTPS) channels. The gate dielectric is a biocompatible and insulating silicon nitride (SiN) or aluminum oxide (Al2O3) layer. The gate electrode is a flexible metal (e.g., graphene, indium tin oxide (ITO), or gold). Source/drain regions are created by localized doping of the thin-film silicon, with a selectively grown silicon-germanium-carbon (SiGeC) alloy layer (e.g., 10% Ge, 1% C) epitaxially formed in recessed regions. This SiGeC layer is engineered to induce a finely tuned tensile or compressive stress in the channel, depending on the desired carrier mobility characteristics for specific sensing elements. The SiGeC layer forms a protruding structure. The space between the protruding SiGeC layer and the gate sidewall (e.g., PECVD SiO2) is filled with a bio-inert, compliant polymer (e.g., Parylene, PDMS) as the stress-relief film. A global encapsulation layer of biocompatible silicon carbide (SiC) or Parylene-C, which provides mechanical protection and acts as a stress insulating film, covers the entire device. The polymer stress-relief film decouples the external encapsulation stress from the sensitive thin-film channels, ensuring stable and reliable sensor operation within biological environments.

graph TD
    A[Flexible Polyimide Substrate] --> B(Thin-Film Si Active Region)
    B --> C{Bio-Integrated MISFET}
    C --> D[Gate Insulating Film (SiN/Al2O3)]
    D --> E[Flexible Metal Gate Electrode (Graphene/ITO/Au)]
    E --> F[Gate Sidewall (PECVD SiO2)]
    B --> G[Recessed S/D Region]
    G --> H[Epitaxial SiGeC Layer (Protruding)]
    H -- Forms Bio-Space --> I[Biocompatible Polymer (Parylene/PDMS)]
    I -- Compliant Stress-Relief --> J[Global Encapsulation / Stress Insulating Film (Biocompatible SiC/Parylene-C)]
    E -- Channel --> K[Thin-Film Si Channel]
    H -- Tuned Stress --> K
    J -- Encapsulation Stress --> H

Derivative 7: Cross-Domain Application - Radiation-Hardened Aerospace Control Unit

Enabling Description:
A semiconductor device for radiation-hardened control units in aerospace applications, built on a silicon-on-sapphire (SOS) substrate for its inherent radiation tolerance. The MISFETs are designed with a gate insulating film of high-purity, radiation-tolerant silicon dioxide (SiO2) and a radiation-hardened polysilicon or metal gate (e.g., refractory metal such as Tungsten). The sidewalls are composed of a radiation-hardened nitride (e.g., low-hydrogen SiN). Source/drain regions are formed by ion implantation and subsequent annealing in trenches, followed by selective epitaxial growth of a high-temperature stable, radiation-tolerant silicon-germanium (SiGe) alloy (e.g., up to 25% Ge) to induce specific compressive stresses in the channel region. This SiGe layer is grown to protrude above the substrate surface. The space between the protruding SiGe layer and the gate sidewall is filled with a radiation-tolerant porous silicon dioxide (p-SiO2) film, providing both stress relief and reduced charge collection volume to mitigate single-event effects (SEE). A global stress insulating film of radiation-hardened silicon nitride (SiN), which can also act as an etch stop and provides additional radiation shielding, covers the entire device. The porous SiO2 stress-relief film, in conjunction with the SiGe, ensures stable performance under intense radiation exposure by buffering mechanical stresses that could otherwise lead to device degradation or parameter shifts.

graph TD
    A[Silicon-On-Sapphire (SOS) Substrate] --> B(Active Si Layer)
    B --> C{Radiation-Hardened MISFET}
    C --> D[Gate Insulating Film (Rad-Hard SiO2)]
    D --> E[Radiation-Hardened Gate (Poly-Si/W)]
    E --> F[Rad-Hard SiN Sidewall]
    B --> G[Trench S/D Region]
    G --> H[Epitaxial Rad-Hard SiGe Layer (Protruding)]
    H -- Forms Space --> I[Porous SiO2 (Stress-Relief & SEE Mitigation)]
    I -- Buffers Radiation-Induced Stress --> J[Global Stress Insulating Film (Rad-Hard SiN)]
    E -- Channel --> K[Channel Region (Under Radiation)]
    H -- Compressive Stress --> K
    J -- Global Stress --> H

Derivative 8: Integration with Emerging Tech - AI-Optimized Adaptive Stress Management

Enabling Description:
A semiconductor device featuring an array of MISFETs, each integrated with embedded micro-electromechanical systems (MEMS) strain gauges and local heating elements, all controlled by an on-chip AI optimization unit. The MISFETs are fabricated on a silicon substrate with gate stacks comprising high-k dielectrics and metal gates. Source/drain regions contain epitaxially grown SiGe or SiC layers in trenches, with protruding portions designed to induce initial fixed stresses. The crucial innovation lies in the dynamic stress-relief film. The space between the protruding S/D and the sidewall is filled with a thermomechanically tunable polymer composite (e.g., a shape-memory polymer or a polymer with embedded piezoelectric nanoparticles). This composite's mechanical properties (e.g., Young's modulus, stress absorption) can be precisely altered via local heating elements or electric fields. An AI controller, utilizing real-time performance feedback from integrated channel mobility sensors and MEMS strain gauges, continuously monitors the effective stress on each MISFET channel. Based on this data and predictive models, the AI dynamically adjusts the temperature or electric field applied to the tunable polymer composite stress-relief films, and potentially the global stress insulating film (which might also be thermomechanically tunable, e.g., a stress-tuneable SiN). This allows for adaptive, real-time optimization of carrier mobility and device performance across varying operational conditions (e.g., temperature fluctuations, aging effects), significantly extending the operational envelope and lifespan.

graph TD
    A[Semiconductor Substrate (Si)] --> B(MISFET Array)
    B --> C[Gate Stack (High-k/Metal)]
    C --> D[Gate Sidewall]
    B --> E[Trench S/D w/ Strained Epi (Protruding)]
    E -- Space --> F[Thermomechanically Tunable Polymer Composite (Stress-Relief)]
    F -- Local Heating/E-Field --> G[Local Heating Element / Electrodes]
    B --> H[Channel Mobility Sensors / MEMS Strain Gauges]
    H --> I[On-Chip AI Optimization Unit]
    I -- Feedback & Control --> G
    B --> J[Global Stress Insulating Film (Thermomechanically Tunable)]
    E -- Initial Fixed Stress --> K[Channel Region]
    F -- Adaptive Stress Mgmt --> K
    J -- Global Stress --> K

Derivative 9: Integration with Emerging Tech - IoT Edge Device with Self-Optimizing Transistors

Enabling Description:
A low-power IoT edge device integrating MISFETs with self-optimizing stress profiles. Each MISFET features a silicon compound layer (e.g., SiGe for p-type, SiC for n-type) in its source/drain region, which is formed in a trench and protrudes above the substrate surface to apply a primary stress. The space between this protruding source/drain and the gate sidewall is filled with a reconfigurable dielectric stress-relief film, capable of undergoing controlled structural changes (e.g., phase transition, selective densification/porosification via localized annealing or chemical treatment) to dynamically adjust its stress buffering capacity. An integrated array of pico-power IoT sensors monitors environmental factors (temperature, humidity, vibration) and device performance metrics (leakage current, drive current). A lightweight, on-chip machine learning (ML) inference engine, pre-trained on a vast dataset of stress-performance correlations, analyzes this sensor data. Based on the predicted optimal stress profile for current conditions, the ML engine triggers localized micro-actuators or thermal elements to reconfigure the stress-relief film. This enables continuous, autonomous fine-tuning of individual transistor performance for maximum energy efficiency or throughput, adapting to dynamic workloads and environmental shifts without external intervention. The global stress insulating film is a standard PECVD SiN layer, providing baseline tensile stress.

graph TD
    A[Semiconductor Substrate] --> B(IoT MISFET Array)
    B --> C[Gate Stack]
    C --> D[Gate Sidewall]
    B --> E[Trench S/D w/ Strained Epi (Protruding)]
    E -- Space --> F[Reconfigurable Dielectric (Stress-Relief)]
    F -- Local Actuators/Thermal --> G[Micro-Actuators / Thermal Elements]
    B --> H[Pico-Power IoT Sensors (Temp, Humidity, Vibration, Perf)]
    H --> I[On-Chip ML Inference Engine]
    I -- Control Signal --> G
    B --> J[Global Stress Insulating Film (PECVD SiN)]
    E -- Primary Stress --> K[Channel Region]
    F -- Self-Optimizing Stress --> K
    J -- Baseline Stress --> K

Derivative 10: The "Inverse" or Failure Mode - Graceful Degradation & Low-Power Redundancy

Enabling Description:
A semiconductor device designed for mission-critical applications where graceful degradation and continued low-power operation are paramount, such as in remote sensor nodes or automotive safety systems. The device incorporates primary MISFETs with standard stress-engineered source/drain regions (e.g., SiGe in trenches with protruding portions) and silicon oxide stress-relief films in the sidewall spaces, covered by a tensile silicon nitride stress insulating film. Alongside these primary transistors, redundant, lower-performance MISFETs are integrated. These redundant transistors feature source/drain regions that intentionally omit the protruding silicon compound layer, or use a significantly thinner, less strained version. Crucially, the stress-relief film in these redundant transistors is made of a material designed to be selectively sacrificial (e.g., a highly porous carbon-doped oxide) which can be rapidly and electrically induced to collapse or be removed, thereby creating an air gap or a more compliant film post-fabrication. Upon detection of a failure or performance degradation in a primary MISFET (e.g., via increased leakage, reduced drive current), or when transitioning to an extreme low-power mode, the device's control logic selectively activates the redundant MISFETs. Simultaneously, it triggers the controlled collapse/removal of the sacrificial stress-relief film in these redundant devices. This action is designed to reduce any localized parasitic stresses or to create a more efficient low-power operating environment by further isolating the channel region from the global stress insulating film, albeit with a trade-off in peak performance. The stress insulating film is designed to remain intact, providing structural integrity.

stateDiagram
    [*] --> NormalOperation
    NormalOperation --> PrimaryMISFETActive
    NormalOperation --> LowPowerMode : External Command
    NormalOperation --> FailureDetected : Sensor Input
    PrimaryMISFETActive --> FailureDetected : Degradation
    FailureDetected --> ActivateRedundantMISFETs
    ActivateRedundantMISFETs --> ReconfigureStressRelief : Initiate Collapse/Removal
    ReconfigureStressRelief --> RedundantMISFETActive : Low Power/Reduced Functionality
    LowPowerMode --> ActivateRedundantMISFETs : Conserve Energy
    RedundantMISFETActive --> [*] : System Shutdown

Derivative 11: The "Inverse" or Failure Mode - Thermally-Activated Self-Healing/Stress-Reset

Enabling Description:
A semiconductor device incorporating MISFETs designed with thermally-activated stress management for self-healing or performance reset. The MISFETs feature conventional gate stacks and trench-based source/drain regions containing a silicon compound layer (e.g., SiGe), with a protruding portion. The space between the protruding S/D and the sidewall contains a stress-relief film made of an engineered shape-memory alloy (SMA) or a specific viscoelastic polymer composite that exhibits a glass transition temperature (Tg) within a recoverable range (e.g., 200-400°C). Over time, device operation and thermal cycling can induce irreversible plastic deformation or stress relaxation, leading to performance degradation. Upon detection of such degradation (e.g., via embedded strain sensors or performance monitoring circuits), the device initiates a localized thermal anneal cycle, raising the temperature of the affected region above the SMA's transition temperature or the polymer's Tg. During this anneal, the SMA/polymer stress-relief film attempts to return to its original shape or relax induced stresses, effectively "resetting" its stress-buffering capacity. This action can release accumulated parasitic stresses or restore the designed stress profile, partially or fully recovering device performance. The global stress insulating film (e.g., SiN) is formulated to be stable and minimally affected by these localized anneal cycles, ensuring its overall structural integrity and desired global stress contribution.

sequenceDiagram
    participant Device
    participant Embedded_Sensors
    participant Control_Logic
    participant Local_Heater
    participant Stress_Relief_Film
    Device->>Embedded_Sensors: Monitor Performance/Stress
    Embedded_Sensors->>Control_Logic: Report Degradation
    Control_Logic->>Local_Heater: Activate Local Anneal
    Local_Heater->>Stress_Relief_Film: Apply Heat (T > Tg/SMA_Transition)
    Stress_Relief_Film->>Stress_Relief_Film: Stress Relaxation / Shape Memory Recovery
    Stress_Relief_Film->>Control_Logic: (Implicit) Stress Profile Reset
    Control_Logic->>Device: Performance Partially Recovered

---

Combination Prior Art Scenarios

1. US Patent 8907425 + Open-Source FinFET Standard:

• Scenario: Combining the stress engineering principles of US8907425 with a FinFET (Fin Field-Effect Transistor) architecture, which is a widely adopted open-source standard in modern semiconductor manufacturing (e.g., described in ITRS roadmap and various academic/industry whitepapers).
• Description: A semiconductor device employs a FinFET structure, where the channel is formed on a vertical fin. The source/drain regions are formed by etching recesses in the fin and performing selective epitaxial growth (SEG) of a silicon compound layer (e.g., SiGe for pFETs, SiC for nFETs) around the fin. In this combination, the silicon compound layer is grown such that it partially encapsulates the base of the fin and protrudes above the original fin height, forming a "raised" source/drain around the fin. A stress-relief film (e.g., a low-k dielectric like SiOCH or an air gap) is formed in the narrow trenches or spaces between the protruding SiGe/SiC S/D regions and the fin sidewall/gate electrode. A global stress insulating film (e.g., tensile SiN) then covers the entire FinFET structure. The protruding SiGe/SiC applies beneficial stress to the fin channel, while the stress-relief film isolates the fin channel from detrimental stresses from the global stress insulating film. This combination adapts the planar stress mitigation technique to the 3D FinFET geometry.

2. US Patent 8907425 + Open-Source RISC-V Microprocessor Architecture:

• Scenario: Applying the stress-engineered MISFETs of US8907425 within the fabrication process of a processor adhering to the open-source RISC-V instruction set architecture (ISA) standard.
• Description: A System-on-Chip (SoC) implementing a RISC-V processor core (e.g., RV64GC variant). The core logic, including key execution units, registers, and cache memories, utilizes MISFETs whose performance is enhanced through the stress engineering techniques described in US8907425. Specifically, the p-type MISFETs within the RISC-V processor are fabricated with recessed source/drain regions epitaxially filled with protruding SiGe layers to induce compressive stress. A silicon oxide stress-relief film is deposited in the space between the protruding SiGe and the gate sidewall. Concurrently, n-type MISFETs in the same RISC-V processor might use a global tensile stress insulating film, which is then prevented from negatively impacting the p-type devices by the stress-relief film. The fabrication method follows Claim 16, ensuring the correct placement of these stress-modulating layers. This allows for higher clock speeds, lower power consumption, and improved overall performance for RISC-V based computing elements.

3. US Patent 8907425 + Open-Source MEMS Inertial Sensor Standard:

• Scenario: Integrating the stress-engineered MISFETs of US8907425 into the readout and control circuitry of an open-source standard MEMS (Micro-Electro-Mechanical System) inertial sensor, such as an accelerometer or gyroscope.
• Description: A MEMS device, such as a capacitive accelerometer, utilizes a proof mass and sensing electrodes, with the readout and control electronics integrated on the same chip. The MISFETs in the integrated readout circuitry (e.g., amplifiers, ADCs) are fabricated using the stress engineering techniques of US8907425. This involves creating p-type MISFETs with trench-formed, protruding SiGe source/drain regions and a stress-relief film (e.g., low-k dielectric) in the sidewall space, covered by a tensile stress insulating film. The enhanced drive capability and reduced performance variability due to stress in these MISFETs improve the signal-to-noise ratio and stability of the MEMS sensor's output, leading to higher precision and accuracy. The use of the stress-relief film is particularly critical for MEMS applications where any unintended stress can cause warping or drift in the mechanical structures. The MISFETs here serve as an integral part of the signal conditioning path from the mechanical transducer element, directly impacting the overall sensor performance.