Obviousness

Based on the information provided within the US Patent 8796779 document, particularly the description of the background art and the inventive step, a robust obviousness challenge under 35 U.S.C. § 103, using only the explicitly cited prior art, is difficult to construct. The patent itself outlines the limitations of existing methods and the novelty of its solution.

Conventional Prior Art (from US8796779 Background):

1. Conventional Semiconductor Device Fabrication Method (FIGS. 11-13): This method describes forming a complementary metal insulator semiconductor (CMIS) device with n-type and p-type MIS transistors. Key features include:

   • A gate insulating film (122a, 122b) comprising an interface layer (102a, 102b, silicon dioxide), a high-k film (103a, 103b, HfO2), and a cap film (104a, 104b).
   • A gate electrode (123a, 123b) comprising a metal film (106a, 106b) and a polysilicon film (107a, 107b).
   • Formation of extension regions (108a, 108b) and sidewall spacers (111a, 111b, including a silicon dioxide film 109a/b and a silicon nitride film 110a/b) [cite: US8796779B2, Column 3, lines 49-65].
   • Limitation: This conventional method "allows nMIS transistors to have only one work function and pMIS transistors to have only one work function" [cite: US8796779B2, Column 4, lines 49-50].

2. T. Schram, et al., Novel Process To Pattern Selectively Dual Dielectric Capping Layers Using Soft-Mask Only, Symp. On VLSI technology, 44 (2008): This reference is cited for "reducing an equivalent oxide thickness (EOT) by means of use of, instead of the silicon dioxide film, a so-called high dielectric constant insulating film such as an HfO2 film as the gate insulating film, and by employing a so-called metal inserted poly silicon (MIPS) structure" [cite: US8796779B2, Column 2, lines 36-47]. It also mentions the patterning of "Selectively Dual Dielectric Capping Layers" [cite: US8796779B2, Column 2, lines 42-43].

Inventive Concept of US8796779 (Claims 1, 7, 14):

The core invention addresses the problem of forming transistors of the same conductivity type with different effective work functions on a single semiconductor substrate. It achieves this by:

• Providing a first MIS transistor with an interface layer thicker than that of a second MIS transistor of the identical conductivity type (Claim 1).
• A method for fabricating this, which includes a critical step (c) of "increasing the thickness of the interface layer of the first gate insulating film in a selective manner, after the step (b)" (Claim 7).
• Specifically, this selective increase is performed by, after covering the gate electrodes with an insulating film, selectively etching a portion of the insulating film covering the first gate electrode, and then selectively oxidizing the exposed interface layer to increase its thickness (Claim 14). This results in different insulating spacer thicknesses (thinner offset spacers allowing oxidation, thicker underlying spacers preventing it) [cite: US8796779B2, Column 5, lines 52-67; Column 6, lines 58-67].

Obviousness Analysis:

A combination of prior art references is considered obvious if a person having ordinary skill in the art (POSA) would have been motivated to combine or modify them to arrive at the claimed invention with a reasonable expectation of success.

Differences from the Prior Art:

The primary difference between the conventional method (FIGS. 11-13) and the claimed invention lies in the ability to create multiple transistors of the same conductivity type with different effective work functions by selectively increasing the interface layer thickness after gate electrode formation. The conventional method explicitly lacks this capability.

Specifically, the conventional method:

• Does not teach forming interface layers of different thicknesses for transistors of the same conductivity type.
• Does not teach selectively oxidizing an interface layer after gate structure patterning.
• Does not teach the use of differential insulating spacer thicknesses (e.g., thin offset spacers vs. thick underlying spacers) as a mechanism to enable selective post-patterning oxidation of the interface layer.

Schram et al. generally discusses high-k films and MIPS structures for EOT reduction and mentions "selectively Dual Dielectric Capping Layers." While "selective" dielectric processing is known, Schram's teaching is focused on forming different initial dielectric capping layers, not on post-patterning selective thickening of an interface layer via oxidation.

Motivation to Combine or Modify:

The patent explicitly states the problem: the conventional method's inability to achieve multiple work functions for same-conductivity-type transistors limits integrated circuit performance by preventing the maximization of driving force at various threshold voltages [cite: US8796779B2, Column 4, lines 43-50].

The inventors themselves considered what might appear to be obvious solutions for adjusting work function, such as:

• Changing the thicknesses of nMIS and pMIS cap films.
• Designing transistors with different types of metal electrodes.
  However, they found these methods "not to be practical because they consisted of significantly increased number of steps" [cite: US8796779B2, Column 4, lines 59-66]. This statement indicates that these more direct approaches were already considered and deemed unsatisfactory or impractical by those skilled in the art.

The patent then states that "As a result of further studies, the inventors have found... increasing the thickness of an interface layer... by means of selective oxidation which is performed after formation of the gate structures" [cite: US8796779B2, Column 4, line 67 - Column 5, line 4]. This phrasing suggests that the solution was not immediately apparent but rather a result of further investigation.

A POSA, faced with the problem outlined, might know that interface layer thickness affects EOT and thus work function. However, the motivation to:

1. Counter-intuitively thicken the interface layer (when the general trend in the art is often to reduce EOT).
2. Perform this thickening selectively after gate electrode formation.
3. Utilize selective oxidation as the mechanism.
4. Achieve this selectivity by strategically varying the thickness of temporary insulating spacers (e.g., thin offset spacers allowing oxidation vs. thick underlying spacers preventing it).
   ...is not taught or suggested by the conventional method or the Schram reference. The conventional method uses uniform spacer formation, and Schram is concerned with initial selective deposition, not post-patterning selective modification using differential masking.

Conclusion:

Without additional specific prior art references that teach or suggest the selective thickening of the interface layer after gate electrode formation using differential insulating spacers to enable selective oxidation for the purpose of tuning work functions in same-conductivity-type transistors, the claims of US8796779 would likely not be considered obvious under 35 U.S.C. § 103, based solely on the prior art presented within the patent itself. The patent's own disclosure highlights the non-obvious nature of its solution by describing the impracticality of more direct alternatives and presenting its method as a result of "further studies."