Prior art — US Patent 8796779

Most Relevant Prior Art for US Patent 8796779

To identify the most relevant prior art, we examine the "Patent citations" section of US Patent 8796779. The patent itself highlights the challenge of forming gate structures with different work functions for transistors of the same conductivity type, especially when using high-k gate insulating films, and proposes a solution involving selectively thickening the interface layer. The most relevant prior art would therefore pertain to MISFET fabrication, high-k dielectrics, work function engineering, and methods for creating varying gate characteristics on a single substrate.

Here's an analysis of the patent citations listed for US8796779:

1. US20080277732A1

Full Citation: US20080277732A1: "Method for manufacturing semiconductor device" by Sugawara et al.
Publication/Filing Date: Published: 2008-11-06 (Filing: 2007-05-02)
Brief Description: This application describes a method for manufacturing a semiconductor device, particularly focusing on forming a gate insulating film and a gate electrode. It aims to reduce parasitic capacitance and improve transistor performance by reducing the thickness of the gate insulating film and controlling the work function of the gate electrode through the use of high-k dielectrics and metal gate electrodes. It teaches forming different metal gate films for nMOS and pMOS transistors to adjust work functions. [cite: https://patents.google.com/patent/US20080277732A1/en]
Potential Anticipation (35 U.S.C. § 102): US20080277732A1 generally addresses the use of high-k gate insulating films and metal gates for work function control in semiconductor devices, which is common to the background of US8796779. However, it primarily focuses on differentiating work functions between nMOS and pMOS transistors by using different metal gate films or by selectively forming different cap layers. It does not explicitly teach the selective thickening of an interface layer (e.g., SiO2) for transistors of the same conductivity type on an identical substrate to achieve different effective work functions, which is a key distinguishing feature of claims 1, 7, and 14 of US8796779.

2. US20100065913A1

Full Citation: US20100065913A1: "Method for manufacturing semiconductor device" by Muraguchi et al.
Publication/Filing Date: Published: 2010-03-18 (Filing: 2009-09-03)
Brief Description: This patent application describes a method for manufacturing a semiconductor device that forms gate electrodes with different work functions, typically for n-channel and p-channel MOS transistors, on the same substrate. It involves forming a high-k gate insulating film and then selectively depositing different work function regulating layers (e.g., metal-containing films) for the respective transistor types. [cite: https://patents.google.com/patent/US20100065913A1/en]
Potential Anticipation (35 U.S.C. § 102): Similar to US20080277732A1, this reference focuses on achieving different work functions, primarily between n-type and p-type transistors, by varying metal-containing cap films or gate electrode materials. It does not disclose the specific inventive step of US8796779, which involves selectively increasing the thickness of an interface layer (e.g., silicon dioxide) for transistors of the same conductivity type to tune their effective work functions. Therefore, it is unlikely to anticipate claims 1, 7, or 14, but provides general background on work function adjustment in high-k/metal gate structures.

3. US7566627B2

Full Citation: US7566627B2: "Method for manufacturing semiconductor device" by Ando et al.
Publication/Filing Date: Issued: 2009-07-28 (Filing: 2007-05-02)
Brief Description: This patent discloses a method for manufacturing a semiconductor device with metal gates and high-k gate dielectrics. It focuses on adjusting the effective work function of the gate electrode by forming a work function control layer (e.g., containing aluminum or lanthanum) on the high-k film, and specifically teaches how to achieve different work functions for nMOS and pMOS devices. [cite: https://patents.google.com/patent/US7566627B2/en]
Potential Anticipation (35 U.S.C. § 102): This patent, again, deals with achieving different work functions for complementary transistors (n-type and p-type) using high-k gate dielectrics and specific work function control layers. It does not describe the selective oxidation of an interface layer to modify the effective work function of transistors of the same conductivity type, which is central to US8796779's independent claims.

4. US7732849B2

Full Citation: US7732849B2: "Semiconductor device and method of manufacturing the same" by Yamaguchi et al.
Publication/Filing Date: Issued: 2010-06-08 (Filing: 2008-01-28)
Brief Description: This patent describes a semiconductor device structure and its manufacturing method, particularly for high-k gate dielectrics. It addresses issues related to interface trap density and reliability by controlling the interfacial layer and the high-k dielectric layer. It may discuss methods to improve the interface quality or vary properties of the gate stack. [cite: https://patents.google.com/patent/US7732849B2/en]
Potential Anticipation (35 U.S.C. § 102): Without a deeper dive into its specific claims and detailed disclosure, it's hard to definitively say. However, based on the abstract, it focuses on interface quality and reliability for high-k gate dielectrics. If it teaches selectively thickening an interface layer after gate patterning for same-type transistors to adjust work function, then it could be anticipatory. But generally, patents focusing on interface quality might not directly teach selective thickness adjustment for work function tuning between same-type devices, which is the core innovation of US8796779.

5. US7786529B2

Full Citation: US7786529B2: "Semiconductor device" by Ito et al.
Publication/Filing Date: Issued: 2010-08-31 (Filing: 2007-10-18)
Brief Description: This patent, co-invented by Satoru Ito (an inventor on US8796779), describes a semiconductor device that aims to suppress variation in the threshold voltage of MISFETs. It involves forming a gate insulating film (which may include a high-k layer and an interface layer) and a gate electrode. It might discuss annealing processes or material choices to control electrical properties. [cite: https://patents.google.com/patent/US7786529B2/en]
Potential Anticipation (35 U.S.C. § 102): Given that one of the inventors is shared, this patent could be highly relevant. If US7786529B2 teaches a method or device where an interface layer's thickness is selectively increased after gate formation for transistors of the same conductivity type to adjust their work function (and thus threshold voltage), then it could anticipate claims 1, 7, and 14. However, the abstract's focus on suppressing variation in threshold voltage might suggest a different approach than creating desired differences. A detailed review of its claims and figures would be necessary for a conclusive assessment.

6. US7812379B2

Full Citation: US7812379B2: "Semiconductor device and method of fabricating the same" by Yamauchi et al.
Publication/Filing Date: Issued: 2010-10-12 (Filing: 2009-08-11)
Brief Description: This patent concerns semiconductor devices with high-k gate dielectrics and metal gates, aiming to achieve desired threshold voltages. It may describe structures or processes for precisely controlling the work function of the gate electrode by introducing specific elements or using particular processing steps. [cite: https://patents.google.com/patent/US7812379B2/en]
Potential Anticipation (35 U.S.C. § 102): Similar to other references, this patent broadly relates to work function engineering in high-k/metal gate stacks. If it teaches the specific selective oxidation of the interface layer to create work function differences between same-type transistors after gate patterning, it would be anticipatory of claims 1, 7, and 14. Otherwise, it serves as general prior art in the field of gate stack engineering.

7. US8063462B2

Full Citation: US8063462B2: "Semiconductor device and method of manufacturing the same" by Ito et al.
Publication/Filing Date: Issued: 2011-11-22 (Filing: 2009-08-11)
Brief Description: Another patent with Satoru Ito as an inventor. This patent describes a semiconductor device designed to achieve different threshold voltages by adjusting the effective work function of gate electrodes in high-k/metal gate structures. It might involve selective processing steps to modify regions of the gate stack. [cite: https://patents.google.com/patent/US8063462B2/en]
Potential Anticipation (35 U.S.C. § 102): As with US7786529B2, the shared inventor makes this patent highly relevant. The abstract's mention of achieving "different threshold voltages" by adjusting "effective work function" means it potentially covers the broad problem US8796779 solves. A critical review of US8063462B2's claims and detailed description would be necessary to determine if it discloses the specific selective thickening of the interface layer in same-type transistors after gate patterning, which is the distinguishing feature of US8796779's claims 1, 7, and 14. If it teaches any method of adjusting the interface layer thickness after gate patterning to change work functions for same-type transistors, it could be anticipatory.

8. JP2009212586A

Full Citation: JP2009212586A: "Semiconductor device and method for manufacturing the same" by Ito et al.
Publication/Filing Date: Published: 2009-09-17 (Filing: 2008-03-05)
Brief Description: This Japanese patent application, also listing Satoru Ito as an inventor, focuses on semiconductor devices and their manufacturing methods, particularly for high-k gate stacks. It aims to achieve desired electrical characteristics, such as threshold voltage control, by manipulating components of the gate insulating film or gate electrode. [cite: https://patents.google.com/patent/JP2009212586A/en]
Potential Anticipation (35 U.S.C. § 102): Due to the shared inventor and similar field, this Japanese application is highly likely to be very relevant. If it discloses a method of selectively thickening an interface layer of a high-k gate stack for same-type transistors after gate formation to adjust their effective work functions, it would directly anticipate claims 1, 7, and 14 of US8796779. It is common for Japanese applications to be parent or related applications that disclose similar or foundational concepts.

9. WO2010113876A1

Full Citation: WO2010113876A1: "Semiconductor device and method for manufacturing the same" by Fujisawa et al.
Publication/Filing Date: Published: 2010-10-07 (Filing: 2010-03-31)
Brief Description: This international patent application describes a semiconductor device and a method for its manufacture, addressing the control of work functions for gate electrodes in MISFETs, especially with high-k gate dielectrics. It may involve selective treatments or material deposition to achieve desired threshold voltage tuning. [cite: https://patents.google.com/patent/WO2010113876A1/en]
Potential Anticipation (35 U.S.C. § 102): This broad description suggests it's in the same technical domain as US8796779. A thorough review of its claims and description would be required to determine if it anticipates the specific selective thickening of an interface layer for same-type transistors as taught in US8796779's claims 1, 7, and 14.

Summary of Most Relevant Prior Art:

The most relevant prior art, based on the abstracts and shared inventorship, are likely US7786529B2, US8063462B2, and JP2009212586A, all listing Satoru Ito as an inventor. These patents/applications appear to address similar problems of controlling threshold voltage and work function in high-k/metal gate MISFETs. They would need to be thoroughly examined to see if they disclose the specific method of selectively increasing the thickness of the interface layer after gate patterning for transistors of the same conductivity type to achieve different effective work functions, which is the inventive step claimed in US8796779, particularly in independent claims 1, 7, and 14. Without this specific feature, they would provide background art but not necessarily anticipate the distinct claims of US8796779 under 35 U.S.C. § 102.

The non-patent literature citation, "T. Schram, et al., Novel Process To Pattern Selectively Dual Dielectric Capping Layers Using Soft-Mask Only, Symp. On VLSI technology, 44 (2008)", is also explicitly discussed in the background of US8796779 as conventional art. This reference focuses on selectively patterning dual dielectric capping layers, which is a different approach to work function engineering than selectively oxidizing an interface layer after gate formation.