US 8704762

Patent Summary: US 8,704,762

Title: Display device

Assignee: The patent is currently assigned to Paneltouch Technologies LLC. The original assignee was Panasonic Liquid Crystal Display Co., Ltd.

Inventors: Kouichi Anno, Takumi Sato, Masahiro Teramoto

Filing Date: June 2, 2011

Issue Date: April 22, 2014

Abstract:
A display device includes a coordinate input device including a transparent substrate having a first signal interconnect disposed in a region outside a detection region corresponding to a contact position, a first electrode terminal, a flexible interconnect substrate connected to the first electrode terminal, and a display panel for image display based on a video signal from an external system. The coordinate inputting device has a second signal interconnect disposed outside the first signal interconnect but near the peripheral edge of the transparent substrate, the second signal interconnect surrounding the area where the detection region is included and the first signal interconnect is formed, the second signal interconnect being opened at opposite ends thereof and being connected to respective electrode terminals for inspection at the open ends, and the second signal interconnect is disposed along the peripheral edge portion of three sides of the transparent substrate.

Plain-Language Overview of Independent Claims:

Claim 1: This claim describes a display device that has both a screen for showing images and a touch input system. The key feature is a special wire (a "second signal interconnect") placed around the edge of the touch-sensitive area. This wire is designed to help check for damage, like cracks or chips, at the edge of the display. It's a separate circuit with its own connection points ("electrode terminals for inspection") that can be used to test its continuity. If this outer wire is broken, it's a strong indication that the display's edge may be damaged, which could also affect the main signal wires of the touch screen.

Claim 9: This claim focuses on the display panel itself, rather than the touch input layer. It describes a display with a similar inspection feature. In this case, a special wire (a "fourth signal interconnect") is placed around the perimeter of the active display area. This wire is located outside the normal signal lines that control the pixels. Much like the wire in the first claim, this one has its own terminals for testing. The purpose is the same: to easily detect damage to the substrate of the display panel by checking if this outer wire has been broken.

As of early 2025, this patent is the subject of litigation. Paneltouch Technologies LLC has filed a patent infringement lawsuit against BOE Technology Group Co., Ltd. in the U.S. District Court for the Eastern District of Texas (Case 2:25-cv-00245). My search of the CAFC 2026 dockets did not reveal any appeals related to this case at this time; however, given the district court filing date, any potential appeal would likely not appear in the 2026 docket yet. No other litigation involving this specific patent was found in the CAFC 2026 dockets.

As of my analysis on April 26, 2026, there is one known litigation involving U.S. Patent No. 8,704,762.

Details of the litigation are as follows:

Case: Paneltouch Technologies LLC v. BOE Technology Group Co., Ltd.

• Plaintiff: Paneltouch Technologies LLC
• Defendant: BOE Technology Group Co., Ltd.
• Jurisdiction: U.S. District Court for the Eastern District of Texas
• Case Number: 2:25-cv-00245
• Filing Date: February 28, 2025
• Status: Closed on April 1, 2026

In this case, Paneltouch Technologies LLC alleged that BOE Technology Group Co., Ltd. infringed on five patents, including the '762 patent. The complaint specified that the alleged infringement was related to "the BOE OLED panel supplied to Valve and included in the Steam Deck" and "the BOE display/touch panel supplied to Amazon and included in the Amazon Fire HD10 tablet." The case was assigned to Judge Rodney Gilstrap.

Based on the patent's history, here is an analysis of the AIA trial proceedings concerning US patent 8,704,762 for a defendant.

Proceedings Overview

One AIA trial proceeding, IPR2025-01482, has been filed against US patent 8,704,762; the Patent Trial and Appeal Board (PTAB) exercised its discretion to deny institution of the trial. Consequently, the patent's validity was not reviewed on the merits, all claims survived the challenge, and a defendant today faces a patent that has not been weakened or narrowed by a PTAB trial.

IPR2025-01482 — BOE Technology Group Co., Ltd. v. Paneltouch Technologies LLC

• Type: Inter Partes Review
• Filed: 2025-09-18
• Status: Discretionary Denial. This means the PTAB declined to institute a trial for procedural reasons, not because the petitioner's invalidity arguments were found to be weak. The patent claims remain unchanged.
• Judge Panel: As the case was terminated before an institution decision on the merits, the panel's detailed analysis is not public, but the case was administered by the PTAB.
• Petition Grounds: A petition for IPR typically asserts that specific patent claims are invalid as anticipated (§ 102) or obvious (§ 103) in view of prior art patents or printed publications. The specific claims and art asserted by BOE Technology are available in the petition filed on the PTAB E2E portal.
• Institution Decision: The proceeding was terminated via a discretionary denial around 2026-04-23. The PTAB often issues such denials under the Fintiv framework, where it declines to institute an IPR because a parallel district court case involving the same patent is too far advanced. Given the record of litigation in the Texas Eastern District Court (2:25-cv-00245), it is highly likely the Board denied institution to avoid duplicative efforts and because the court's trial date was expected to precede the PTAB's deadline for a Final Written Decision.
• Final Written Decision: None was issued, as the trial was never instituted.
• Settlement / Termination: The proceeding was terminated at the institution phase by the PTAB's discretionary denial. This is a procedural victory for the patent owner, not a settlement between the parties.
• Appeal: A decision to deny institution of an IPR is not appealable to the Federal Circuit.
• Defensive Value: This proceeding offers minimal defensive value. No claims were invalidated, and no prior art was adjudicated. It demonstrates that the current patent owner, Paneltouch Technologies LLC, has successfully used the progress of co-pending district court litigation to shield the patent from a validity challenge at the PTAB. Any future petitioner will likely face the same Fintiv-based arguments.

Strategic Summary

Claim Status: All claims of US 8,704,762 remain valid and enforceable. The patent has not been tested on the merits, narrowed, or amended in any PTAB proceeding. All claims are effectively UNTESTED by the PTAB.

Estoppel Landscape: Because the IPR was not instituted, no statutory estoppel under 35 U.S.C. § 315(e) applies. The petitioner, BOE Technology, is not barred from re-challenging the patent in district court or even filing another IPR if circumstances change (e.g., the district court case is stayed). More importantly for a new defendant, there is no estoppel whatsoever, and all prior art-based invalidity grounds remain available for a new PTAB petition or for use in district court.

Pattern Signals: The patent's assignment history shows a transfer to Paneltouch Technologies LLC on 2024-04-27, a likely patent assertion entity. The filing of district court litigation (2025) and the subsequent defensive IPR by the target (BOE Technology) follows a very common pattern. The patent owner's ability to secure a discretionary denial is a significant strategic signal; they have a proven playbook for defeating PTAB challenges by leveraging the speed of the district court docket.

Recommended Next Steps

• Acknowledge that no claims of US 8,704,762 have been invalidated or canceled. Any defense must be built from the ground up, as there is no prior PTAB decision to rely on.
• If considering a new IPR, you must develop a strategy to overcome the same Fintiv arguments that led to the denial of IPR2025-01482. This requires a detailed analysis of the current schedule in the Texas litigation. The window for filing an IPR that the Board will agree to hear may be very narrow or already closed.
• The publicly filed petition for IPR2025-01482 can serve as a useful, though non-binding, starting point for your own invalidity analysis. It reveals a set of prior art and arguments that a well-funded petitioner has already developed.

Inventors

• Kouichi Anno
• Takumi Sato
• Masahiro Teramoto

All inventors listed Panasonic Liquid Crystal Display Co., Ltd. as their assignee at the time of filing. This indicates the invention was created as part of their employment at the company.

Original assignee

The original assignee was Panasonic Liquid Crystal Display Co., Ltd., a joint venture between Panasonic and Hitachi focused on manufacturing liquid crystal display (LCD) panels for various electronic devices. This entity was an operating company that developed and manufactured products embodying the technologies described in its patents.

The display industry underwent significant consolidation. Hitachi Displays merged with entities from Sony and Toshiba to form Japan Display Inc. in 2012. Panasonic Liquid Crystal Display Co., Ltd. eventually ceased independent operations, and its patent assets were reassigned.

Assignment timeline

• 2011-07-21 (executed) / recorded 2011-07-21 — Reel 026779/0146

  • Conveyance: Assignment
  • Assignor: Kouichi Anno, Takumi Sato, Masahiro Teramoto
  • Assignee: Hitachi Displays, Ltd. and Panasonic Liquid Crystal Display Co., Ltd.
  • Correspondent: Noboru Iwasa, Mattingly & Malur, P.C., 1800 Diagonal Rd., Ste 370, Alexandria, VA 22314
  • Context: This is the initial assignment of the invention from the inventors to their employers, a standard procedure.

• 2014-01-13 (executed) / recorded 2014-01-13 — Reel 031853/0746

  • Conveyance: Change of Name
  • Assignor: Hitachi Displays, Ltd.
  • Assignee: Japan Display East, Inc.
  • Correspondent: Antonelli, Terry, Stout & Kraus, LLP, 1300 North Seventeenth Street, Suite 1800, Arlington, VA 22209
  • Context: A corporate name change reflecting industry consolidation.

• 2014-01-13 (executed) / recorded 2014-01-13 — Reel 031853/0749

  • Conveyance: Change of Name
  • Assignor: Japan Display East, Inc.
  • Assignee: Japan Display Inc.
  • Correspondent: Antonelli, Terry, Stout & Kraus, LLP, 1300 North Seventeenth Street, Suite 1800, Arlington, VA 22209
  • Context: Further corporate name change centralizing assets under the Japan Display Inc. brand.

• 2023-11-17 (executed) / recorded 2023-11-17 — Reel 067086/0733

  • Conveyance: Assignment (Nunc Pro Tunc as of 2012-04-01)
  • Assignor: Panasonic Liquid Crystal Display Co., Ltd.
  • Assignee: Panasonic Intellectual Property Corporation of America
  • Correspondent: Panasonic IP Management, 2 Christie Heights Street, Leonia, NJ 07605
  • Context: Internal transfer of patent assets from the original joint venture to Panasonic's dedicated US intellectual property holding company. The nunc pro tunc clause backdates the effective transfer to 2012.

• 2024-03-27 (executed) / recorded 2024-04-27 — Reel 068417/0448

  • Conveyance: Assignment
  • Assignor: Japan Display Inc. and Panasonic Intellectual Property Corporation of America
  • Assignee: Paneltouch Technologies LLC
  • Correspondent: Robert P. Michal, Carter, DeLuca & Farrell, LLP, 576 Broad Hollow Road, Melville, NY 11747
  • Context: Transfer from the original operating companies to a newly formed LLC, signaling a move toward assertion.

Timeline diagram

timeline
    title Ownership of US 8704762
    2011 : Filed and assigned to Hitachi and Panasonic LCD
    2014 : Granted
         : Name changes consolidate ownership to Japan Display Inc
    2023 : Panasonic assets moved to its US IP holding company
    2024 : Assigned to Paneltouch Technologies LLC

NPE / troll-pattern signals

1. Shell-entity transfer — Present. The 2024 assignment moves the patent from operating companies (Japan Display, Panasonic) to Paneltouch Technologies LLC. This LLC has a name suggesting a licensing focus ("-touch Technologies"), was formed shortly before the assignment, and does not appear to have commercial products. This transfer occurred on 2024-03-27 (recorded 2024-04-27) per Reel 068417/0448.

2. Known asserter in the chain — Not present. None of the assignees appear on major public NPE lists as of today's date, 2026-05-13. Paneltouch Technologies is a new entity.

3. Repeat correspondent across the chain — Not present. Each assignment was handled by a different law firm or in-house correspondent. The final transfer to Paneltouch Technologies LLC was recorded by Robert P. Michal of Carter, DeLuca & Farrell, LLP. While this firm is known for patent prosecution and litigation, this is its only appearance in this chain.

4. Cascading transfers — Not present. The transfers are separated by many years. The final transfer is a key event, but it is not part of a rapid series of hand-offs.

5. Pre-litigation transfer — Present. While no litigation has been filed as of 2026-05-13, the transfer to Paneltouch Technologies LLC in March 2024 follows a classic pattern of moving a patent to a dedicated entity immediately before an assertion campaign begins. The transfer from operating companies cleans the title and prepares the patent for monetization through licensing or litigation.

6. Bankruptcy fire-sale — Not present. The transfers resulted from industry consolidation and strategic IP management, not bankruptcy proceedings.

7. Privateering — Unclear. It is possible that Panasonic and/or Japan Display have a financial interest in the assertion activities of Paneltouch Technologies LLC, but there is no public evidence (such as SEC filings) to confirm this arrangement.

8. Defensive aggregator (anti-NPE) — Not present. The chain does not involve any known defensive aggregators.

Verdict

NPE — high confidence

The transfer of this patent from its original creators, Panasonic and Japan Display, to a newly formed entity, Paneltouch Technologies LLC, is a strong indicator of a shift from a defensive/operational posture to an offensive assertion strategy (Reel 068417/0448). This classic "shell-entity transfer" pattern, combined with the timing that suggests preparation for a licensing or litigation campaign ("pre-litigation transfer"), provides high confidence that this patent is now held by a non-practicing entity for the purpose of assertion.

A direct link to the USPTO Assignment Center search for US 8704762 is available for verification: https://assignment.uspto.gov/patent/index.html#/patent/search/result?patentNumber=8704762

Analysis of Prior Art for U.S. Patent 8,704,762

As of the current date, May 13, 2026, the following analysis details the most relevant prior art cited against U.S. Patent 8,704,762, titled "Display device." The analysis focuses on the potential for anticipation of the patent's claims under 35 U.S.C. § 102, which pertains to novelty.

The core invention of US Patent 8,704,762 lies in a display device, which includes a coordinate input device (touch panel) or a display panel, featuring a dedicated signal interconnect placed along the periphery of the substrate. This "second" or "fourth" signal interconnect is designed to surround the primary functional areas (the detection region and its associated "first" signal interconnects). Its purpose is to serve as a diagnostic line; by checking its electrical continuity between two dedicated inspection terminals, one can easily detect physical defects like chipping or cracks at the substrate's edge, which might otherwise be difficult to observe visually after assembly.

Below are the most pertinent prior art references cited during the patent's prosecution and their relevance to the claims.

1. JP 2002-350896 A (Assigned to NEC Corp)

• Full Citation: Japanese Patent Application Publication No. JP 2002-350896 A.
• Publication Date: December 6, 2002.
• Filing Date: May 24, 2001.
• Brief Description: This reference discloses a liquid crystal display (LCD) device with a method for detecting disconnection in common interconnects. It describes connecting common interconnects, which are arranged in parallel, to each other at the peripheral edge portion of the display screen. The design includes an opening at a central portion to facilitate the detection of disconnections in these common lines using an array testing technique.
• Potential Anticipation of Claim(s): This reference was considered by the applicant and is mentioned in the background section of US 8,704,762 (Col. 2, lines 8-15). While it relates to detecting interconnect defects, it does not appear to anticipate the key elements of the independent claims of the '762 patent.
  • Claim 1 of US 8,704,762 requires a separate "second signal interconnect" disposed outside the "first signal interconnect" near the peripheral edge, specifically for inspection of substrate integrity (chipping/cracking). JP 2002-350896 describes a method of testing the functional common interconnects themselves by linking them at the periphery. It does not teach a distinct, surrounding, non-functional line dedicated solely to physical defect inspection. The '762 patent explicitly distinguishes its invention by stating that the method in JP '896 "requires inspection on every signal interconnect, it may take extremely much time" (Col. 2, lines 36-38), whereas its own invention provides a simple pass/fail test for the substrate edge.

2. US 2009/0284483 A1 (Lee et al.)

• Full Citation: U.S. Patent Application Publication No. 2009/0284483 A1, Inventors: Lee, et al., Assignee: LG Display Co., Ltd.
• Publication Date: November 19, 2009.
• Filing Date: May 14, 2008.
• Brief Description: Lee et al. describe a touch screen panel integrated with an LCD. The disclosure includes details on the routing of signal lines and electrodes. It addresses the need for testing and inspection during manufacturing. Specifically, it discloses test lines and pads for evaluating the electrical characteristics of the touch sensor electrodes and their connections.
• Potential Anticipation of Claim(s): This reference is highly relevant as it discusses testing structures within a touch-enabled display.
  • Claim 1 and dependent claims: Lee et al. disclose various test lines and circuits. However, the primary purpose of the test lines described appears to be for checking the electrical properties (shorts, opens) of the functional touch sensor lines (e.g., the Rx and Tx electrodes) rather than a dedicated, peripheral "guard ring" style interconnect for detecting physical substrate damage. The novelty of claim 1 of the '762 patent rests on the specific structural arrangement and purpose of the second signal interconnect: being located outside the functional signal lines, near the peripheral edge, surrounding the functional area, and being used to detect physical chipping or cracking. A detailed review of Lee et al.'s figures and description would be necessary to confirm if it discloses this exact structure and purpose. If its test lines are intermingled with or are part of the functional interconnects, it would not anticipate the claimed invention.

3. JP 11-149097 A (Assigned to Fujitsu Ltd)

• Full Citation: Japanese Patent Application Publication No. JP H11-149097 A.
• Publication Date: June 2, 1999.
• Filing Date: November 21, 1997.
• Brief Description: This patent application discloses a plasma display panel (PDP) that includes a test pattern of wiring on the substrate. The test wiring is designed to check for breaks or short circuits in the signal lines. The test pattern is placed in the non-display area of the panel and can be used to identify manufacturing defects.
• Potential Anticipation of Claim(s): Similar to the other references, this document addresses the problem of defect detection using dedicated test lines.
  • Claims 1 and 2: The key question for anticipation is whether the "test pattern of wiring" in JP 11-149097 A is structurally and functionally equivalent to the "second signal interconnect" and "fourth signal interconnect" of the '762 patent. Claim 1 specifies that the interconnect is "disposed outside the first signal interconnect but near the peripheral edge of the transparent substrate" and that it "surround[s] the area where the detection region is included and the first signal interconnect is formed." If the test wiring in JP '097 is arranged in this specific peripheral, surrounding manner for the purpose of detecting edge defects that could sever the line, it could be considered to anticipate the claim. However, test lines are often designed to check for shorts between adjacent functional lines or opens within them, and may not necessarily form a continuous loop around the periphery as taught by the '762 patent for detecting physical substrate damage.

Summary

The novelty of US Patent 8,704,762 hinges on a specific, elegant solution: a single, continuous conductive loop placed at the outermost edge of the substrate, outside of all functional wiring, whose sole purpose is to act as a tripwire for physical damage. While prior art, including JP 2002-350896, US 2009/0284483 A1, and JP 11-149097 A, discloses various forms of test lines and interconnects for diagnosing electrical faults in display and touch panels, none appear to explicitly teach the precise structure and purpose claimed in the '762 patent. The prior art focuses on testing the integrity of the functional circuits, whereas the '762 patent provides a method for testing the integrity of the substrate itself, thereby indirectly confirming that the functional circuits, which lie inward from the inspection line, are likely undamaged by edge chipping or cracks. Therefore, direct anticipation under 35 U.S.C. § 102 by these references is unlikely, as they do not appear to disclose all elements of the independent claims arranged as specified.

Based on my analysis of the prior art cited on the face of US patent 8,704,762 and other analogous art, the independent claims of the '762 patent would likely be rendered obvious under 35 U.S.C. § 103. The core invention—an additional, dedicated conductive line at the periphery of a substrate for detecting cracks or chips—is a combination of a standard display/touch panel structure with a known testing technique from the broader field of electronics manufacturing.

A person having ordinary skill in the art (PHOSITA) in display and touch panel design circa 2010-2011 would have been familiar with the problem of substrate chipping during manufacturing and handling, which could sever critical signal interconnects. The motivation to find a simple, low-cost method for detecting such damage before final assembly would have been high.

Obviousness Analysis of Independent Claim 1

Claim 1 describes a display device with a coordinate input device (touch panel) that includes a second signal interconnect acting as a dedicated inspection line for detecting substrate damage.

An obviousness rejection of Claim 1 can be formulated based on the combination of a primary reference teaching the general structure of a touch panel and a secondary reference teaching the use of a peripheral crack-detection line.

• Primary Reference: A reference like US 2008/0150912 A1 (Hotelling et al.), which is representative of the state of the art for capacitive touch panels around the priority date of the '762 patent. Hotelling describes the fundamental structure claimed in the '762 patent, including a transparent substrate with detection electrodes, and signal interconnects (first signal interconnect) routed in the border regions outside the active detection area to connect to a flexible interconnect substrate.
• Secondary Reference: US 6,249,124 B1 (Tumey et al.) teaches a method for testing for cracks in the ceramic substrate of an electronic device. Tumey explicitly discloses forming a conductive trace (a "crack detection line") along the perimeter of the substrate. This line is connected to its own test pads. The principle is that a crack in the substrate will sever the line, creating a detectable open circuit.

Combination and Motivation

A PHOSITA, starting with the touch panel design of Hotelling, would be aware of the problem articulated in the '762 patent's own background section: "If chipping or crack is formed at the end of the glass substrate at the cutting step or during handling... a problem with interconnect defect arises" (Column 1, lines 30-34). This was a well-known manufacturing yield issue.

The PHOSITA would be motivated to find a reliable method to screen for such defects. The solution taught by Tumey—using a sacrificial trace along the substrate edge—is a direct and analogous solution to this exact problem, albeit in the context of a ceramic IC substrate rather than a glass display substrate. The motivation to combine would be to apply the known testing methodology of Tumey to the known touch panel structure of Hotelling to solve the known problem of detecting peripheral damage.

The implementation would be straightforward:

1. On the same layer as Hotelling's first signal interconnect, a designer would add another trace, the second signal interconnect, following the teaching of Tumey.
2. This new trace would be placed outside the functional first signal interconnect but near the edge of the substrate, as this is the most effective location to detect peripheral chips and cracks, precisely as Tumey teaches.
3. This trace would be connected to its own dedicated "electrode terminals for inspection," again as taught by Tumey, to allow for a simple continuity test (e.g., a resistance measurement).

This combination directly arrives at the invention of Claim 1. There would be a reasonable expectation of success, as forming conductive traces on glass is a fundamental process in display manufacturing.

Obviousness Analysis of Independent Claim 9

Claim 9 describes a display panel (rather than a touch panel) with a fourth signal interconnect serving as a dedicated inspection line. The logic is identical to the analysis for Claim 1.

An obviousness rejection of Claim 9 can be formulated based on the combination of a reference teaching a standard display panel structure and Tumey.

• Primary Reference: A reference such as JP-A-2002-350896 (Abe), cited by the '762 patent, or the general description of an active-matrix LCD panel provided in the '762 patent's background. These references teach a substrate with video and scanning signal lines, a display area, and signal interconnects (third signal interconnect) in the peripheral region connecting to driver circuitry.
• Secondary Reference: US 6,249,124 B1 (Tumey et al.), as described above.

Combination and Motivation

The motivation to combine these references is the same as for Claim 1. The substrate of a display panel is just as susceptible to chipping and cracking during manufacturing as the substrate of a touch panel. The consequences of an undetected crack severing a third signal interconnect (controlling entire rows or columns of pixels) are significant.

A PHOSITA designing the display panel taught by a reference like Abe would be motivated by the same need for improved defect detection. Applying the crack-detection methodology from Tumey to the display panel substrate would be a simple and obvious step to improve manufacturing yield and reliability. The designer would add a fourth signal interconnect along the periphery, outside the functional third signal interconnect, with dedicated test terminals. This would allow for a quick electrical test to confirm the physical integrity of the substrate's edge before the costly process of bonding driver chips and final assembly.

This combination of a standard display panel layout with the testing principle from Tumey would render the structure described in Claim 9 obvious to a person of ordinary skill in the art.

Patent Term and Related Applications for US 8,704,762

As of May 13, 2026, the following details pertain to the patent term and application history for U.S. Patent No. 8,704,762.

Patent Term

• Filing Date: June 2, 2011
• Standard 20-Year Term: The patent term would normally expire on June 2, 2031, which is 20 years from its earliest non-provisional filing date.
• Patent Term Adjustment (PTA): The USPTO has granted a Patent Term Adjustment of 231 days due to administrative delays during the prosecution of the patent application. This adjustment extends the patent's enforceability.
• Patent Term Extension (PTE): There are no Patent Term Extensions for this patent. PTE is typically granted for delays related to regulatory review (e.g., by the FDA) and is not applicable here.
• Projected Expiration Date: After applying the 231-day PTA, the calculated expiration date for US 8,704,762 is January 19, 2032.

Related Applications and Patent Family

The invention disclosed in US 8,704,762 is part of a larger family of patents that stem from the original application (13/151,362). The inventors pursued additional patents through continuation applications, which build upon the parent disclosure.

• Parent Application:

  • Application No.: 13/151,362
  • Filed: June 2, 2011
  • Status: Patented as US 8,704,762

• Continuation Applications (Child Patents):

  • US Patent 9,274,631 (Application No. 14/254,926): This is a continuation of the application for the '762 patent. It was filed on April 17, 2014, and issued on March 1, 2016. It shares the same priority date and will expire on the same date as the parent '762 patent: January 19, 2032.
  • US Patent 9,507,477 (Application No. 15/005,737): This is a continuation of the application for the '631 patent. It was filed on January 25, 2016, and issued on November 29, 2016. It also shares the same priority date and will expire on January 19, 2032.
  • US Patent 9,740,071 (Application No. 15/294,844): This is a continuation of the application for the '477 patent. It was filed on October 17, 2016, and issued on August 22, 2017. As part of the same family, it shares the same priority date and will also expire on January 19, 2032.

This series of continuation patents indicates a strategy by the original assignee to build a portfolio around the core invention, with each subsequent patent potentially covering different aspects or embodiments of the display device inspection technology. All patents in this family are linked by their common priority claim to the initial 2011 application and therefore share the same expiration date.

Defensive Disclosure and Prior Art Generation for US 8,704,762

Document ID: DD-8704762-20260513
Publication Date: 2026-05-13
Subject Matter: Derivative works and improvements upon the inspection interconnect for display devices as described in US Patent 8,704,762.

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Derivatives Based on Claim 1: Coordinate Input Device Inspection Interconnect

Axis 1: Material & Component Substitution

Derivative 1.1: Piezoresistive Polymer Inspection Trace

• Enabling Description: The second signal interconnect is fabricated from a piezoresistive polymer composite, such as carbon-black-infused polydimethylsiloxane (PDMS) or a poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) formulation. Unlike a simple conductive trace which only detects binary open/closed circuits (continuity), this material changes its electrical resistance in response to mechanical stress. The inspection terminals are connected to a high-precision digital multimeter or an ADC-equipped microcontroller. During quality control or device operation, a baseline resistance is measured. A micro-crack or delamination near the substrate edge, even if it does not fully sever the trace, will induce localized strain, causing a measurable change in resistance. This allows for pre-failure detection and characterization of the severity of the defect, rather than a simple go/no-go test. The trace can be screen-printed or inkjet-printed onto the substrate (e.g., third substrate SUB3) in the same process step as other organic electronic components.

• Mermaid Diagram:

  graph TD
      subgraph Piezoresistive Inspection Circuit
          A(Inspection Terminal 1) -->|Baseline R = 10kΩ| B{Piezoresistive Polymer Trace};
          B --> C(Inspection Terminal 2);
          D[Microcontroller with ADC] -- Reads Resistance --> B;
          E{Micro-crack introduces strain} -.-> B;
          B -- Resistance changes to 10.5kΩ --> D;
          D -- Reports Anomaly --> F[System Controller];
      end
  

Derivative 1.2: Embedded Fiber-Optic Loop for Strain and Fracture Detection

• Enabling Description: The second signal interconnect is replaced with a single-mode optical fiber loop embedded or bonded along the periphery of the transparent substrate. One end of the loop is coupled to a light source (e.g., a VCSEL at 850nm), and the other end is coupled to a photodetector. A Fiber Bragg Grating (FBG) is inscribed into the fiber at one or more points along its path. The inspection circuit monitors two parameters:

  1. Light Transmission: A complete fracture of the substrate will sever the fiber, causing a total loss of signal at the photodetector, providing a clear indication of catastrophic failure.
  2. Bragg Wavelength Shift: Mechanical stress or thermal expansion/contraction of the substrate will strain the FBG, causing a shift in the reflected Bragg wavelength (ΔλB). This shift is monitored by a wavelength interrogator. This provides a highly sensitive, non-electrical method for detecting stress concentration points that precede fracture, making it suitable for high-reliability applications and environments with high EMI.

• Mermaid Diagram:

  sequenceDiagram
      participant VCSEL as Light Source (850nm)
      participant Loop as Fiber-Optic Loop with FBG
      participant Interrogator as FBG Interrogator
      participant Photodetector
      participant System
  
      VCSEL->>Loop: Emits Continuous Light
      Loop->>Photodetector: Transmits Light
      activate Photodetector
      Interrogator->>Loop: Monitors Reflected Wavelength (λB)
      activate Interrogator
      System->>System: Baseline: No Stress
      Note over Loop: Substrate bends, creating strain
      Loop-->>Interrogator: Reflected Wavelength Shifts (ΔλB)
      Interrogator-->>System: Reports Strain Anomaly
      Note over Loop: Substrate cracks, severing fiber
      Loop--xPhotodetector: Light transmission ceases
      Photodetector-->>System: Reports Catastrophic Failure
  

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Axis 2: Operational Parameter Expansion

Derivative 2.1: Cryogenic Flexible Display Integrity Monitoring

• Enabling Description: The invention is applied to a flexible polyimide substrate-based OLED display designed for operation in cryogenic environments (-150°C to -200°C), such as in deep-space instrumentation or superconducting quantum computer interfaces. At these temperatures, material embrittlement is a primary failure mode. The inspection interconnect (second signal interconnect) is a multi-trace structure composed of materials with differing coefficients of thermal expansion (CTE), for example, parallel traces of gold (Au) and constantan. As the device is cooled, the differential strain between the traces and the substrate induces a measurable change in the resistance ratio between the two traces. An anomalous reading indicates non-uniform thermal contraction or material fatigue, predicting a potential fracture upon further thermal cycling. The inspection is performed by a four-wire Kelvin sensing method to eliminate contact resistance effects, which can be significant at low temperatures.

• Mermaid Diagram:

  stateDiagram-v2
      [*] --> Unstressed_293K
      Unstressed_293K: R_Au / R_Const = X
      Unstressed_293K --> Cooling
      Cooling --> Stressed_77K: Uniform Contraction
      Stressed_77K: R_Au / R_Const = Y
      Stressed_77K --> Unstressed_293K: Warming
      Cooling --> Anomaly_Detected: Non-uniform stress
      Anomaly_Detected: R_Au / R_Const ≠ Y
      Anomaly_Detected --> Failure_Risk_Flagged
      Failure_Risk_Flagged --> [*]
  

Derivative 2.2: High-Frequency Impedance Monitoring of Inspection Trace

• Enabling Description: Instead of a DC continuity or resistance check, the inspection interconnect is treated as a transmission line. An AC signal in the RF range (e.g., 100 MHz - 1 GHz) is injected into one inspection terminal, and the S-parameters (S11 - return loss, S21 - insertion loss) are measured at the terminals using a vector network analyzer (VNA) circuit integrated into the display driver IC. A micro-crack, even if it doesn't break the DC path, creates a capacitive or inductive discontinuity. This discontinuity causes an impedance mismatch, which is detectable as a significant change in the S-parameters at specific frequencies. Time-Domain Reflectometry (TDR) can be implemented by injecting a fast-rise-time pulse and analyzing the reflection. The timing and shape of the reflection can precisely locate the physical position of the defect along the peripheral trace.

• Mermaid Diagram:

  flowchart LR
      subgraph Test Setup
          A[Signal Generator (100MHz)] --> B(Inspection Terminal 1)
          C(Inspection Terminal 2) --> D[RF Detector/ADC]
      end
      subgraph Substrate
          B --> E{Peripheral Inspection Trace};
          E --> C;
          F(Micro-crack) -- Creates Impedance Mismatch --> E;
      end
      D -- Measures S21 parameter --> G{Analysis Unit};
      G -- Compares to Golden Sample Profile --> H{Pass/Fail/Locate};
  

---

Axis 3: Cross-Domain Application

Derivative 3.1: Aerospace - Smart Skin for Micrometeoroid Impact Detection

• Enabling Description: The display device substrate is replaced with the composite skin panel of a satellite or spacecraft. A grid of peripheral and internal inspection interconnects, analogous to the second signal interconnect, is printed or embedded in a non-conductive layer of the skin. The interconnects are made from a brittle, conductive material. A micrometeoroid or orbital debris (MMOD) impact creates a shockwave that fractures the brittle traces in a localized area. By continuously monitoring the continuity of the grid segments, the system can detect an impact, estimate its location by identifying which traces were severed, and infer the impact energy by the number of fractured traces. This provides real-time structural health monitoring without complex acoustic sensors.

• Mermaid Diagram:

  graph TD
      subgraph Satellite Skin Panel
          direction LR
          A1--Trace Y1---A2
          B1--Trace Y2---B2
          C1--Trace Y3---C2
  
          subgraph Perpendicular Traces
              direction TB
              D1--Trace X1---D2
              E1--Trace X2---E2
              F1--Trace X3---F2
          end
      end
      G(MMOD Impact) -- fractures traces --> X2 & Y2
      H[Continuity Monitor] -- detects open circuits on --> I(X2 & Y2 terminals)
      I --> J[Onboard Computer]
      J -- Triangulates Location --> K(Report: Impact at coordinates X2, Y2)
  

Derivative 3.2: AgTech - Smart Greenhouse Panel Integrity System

• Enabling Description: The concept is applied to large polycarbonate or glass panels used in advanced agricultural greenhouses. The inspection interconnect is a transparent conductive oxide (e.g., ITO, FTO) trace deposited around the perimeter of each panel. These panels are subject to stress from wind, hail, and thermal expansion. A break in a panel, which could compromise the controlled internal environment, severs the trace. Each panel's trace is connected to a central monitoring system via a low-power wireless mesh network (e.g., LoRaWAN). When a break occurs, the panel's node sends an alert with its unique ID, allowing for immediate identification and replacement of the damaged panel, minimizing crop loss.

• Mermaid Diagram:

  classDiagram
  class GreenhouseController {
      +monitorPanels()
      +receiveAlert(panelID)
  }
  class PanelNode {
      <<LoRaWAN>>
      -panelID: string
      -traceContinuity: boolean
      +checkIntegrity()
      +sendAlert()
  }
  class InspectionTrace {
      -isBroken: boolean
  }
  GreenhouseController "1" -- "*" PanelNode : Manages
  PanelNode "1" -- "1" InspectionTrace : Monitors
  

Derivative 3.3: Medical - Implantable Device Hermetic Seal Verification

• Enabling Description: The substrate is the ceramic or titanium casing of an implantable medical device, such as a pacemaker or neurostimulator. The inspection interconnect is a thin-film trace deposited around the hermetic seal joint between the casing halves. The trace runs both on the exterior and interior, connected by a sealed via. After sealing (e.g., by laser welding), the continuity of this trace is verified to confirm the integrity of the weld. Post-implantation, the device can periodically perform a self-check. The ingress of bodily fluids into a compromised seal would corrode and break the trace, providing an early warning of seal failure before moisture damages the critical internal electronics.

• Mermaid Diagram:

  graph TD
      A(Pacemaker Electronics) -- runs periodic check --> B{Trace Terminals}
      subgraph Device Casing
          C(External Trace) -- via --> D(Internal Trace)
          B -- connected to --> C & D
      end
      E(Seal Breach) -- fluid ingress --> F(Corrosion)
      F -- severs trace --> C
      A -- detects open circuit --> G(Transmit Failure Alert to External Monitor)
  

---

Axis 4: Integration with Emerging Tech

Derivative 4.1: IoT-Enabled Self-Reporting Display for Supply Chain

• Enabling Description: The inspection interconnect terminals of the touch panel (or display panel) are connected to an ultra-low-power microcontroller with an integrated NFC (Near Field Communication) or BLE (Bluetooth Low Energy) module. This unit is powered by an energy-harvesting circuit or a small thin-film battery. Throughout the supply chain—from the panel fabrication plant to the OEM assembly line—the integrity of the panel's substrate can be checked wirelessly at each handoff point by simply tapping it with an NFC reader or scanning for its BLE beacon. A detected open circuit (indicating a crack from mishandling) is immediately logged to a cloud database, pinpointing the stage where the damage occurred.

• Mermaid Diagram:

  sequenceDiagram
      participant Fab as Panel Fab
      participant Logistics as Shipping
      participant OEM
      participant Cloud
      Fab->>Logistics: Ship Panel (Integrity OK)
      Logistics->>Logistics: Panel is dropped (Crack occurs)
      OEM->>Logistics: Receives Panel
      OEM->>OEM: Scans Panel with NFC Reader
      Note over OEM: Reader detects open circuit
      OEM->>Cloud: Logs Damaged Panel ID & Timestamp
      Cloud-->>Fab: Notifies of Damage in Transit
  

Derivative 4.2: AI-Driven Predictive Failure Analysis

• Enabling Description: A display device incorporates an array of multiple, parallel inspection interconnects along the periphery, each made of slightly different materials or having different geometries (e.g., varying thickness, serpentine vs. straight). This creates a sensor array that responds differently to stress, temperature, and humidity. An onboard AI/ML model, trained on a dataset of previously failed units, continuously monitors the resistance, capacitance, and thermal drift of all traces in the array. The model recognizes subtle, multi-variate patterns in the data that are precursors to specific failure modes (e.g., corner crack vs. side delamination). The device can then provide a predictive warning to the user, e.g., "Structural stress detected. Avoid flexing device. Backup data now," long before the damage becomes critical.

• Mermaid Diagram:

  flowchart TD
      subgraph Sensor Array
          A[Trace 1 (Au)]
          B[Trace 2 (Ag)]
          C[Trace 3 (ITO)]
      end
      D[Multiplexer & ADC] --> E[Feature Vector (R1, C1, R2, C2, ...)]
      E --> F(Onboard ML Model)
      F -- Pattern Recognition --> G{Failure Mode Prediction}
      G --> H(Corner Crack - 85% Confidence)
      H --> I[User Alert System]
  

---

Axis 5: The "Inverse" or Failure Mode

Derivative 5.1: Fused-Trace for Graceful Degradation

• Enabling Description: The inspection interconnect is designed not just to detect failure, but to trigger a safe-fail mode. It is co-located with a "fuse" trace that controls power to a non-essential but high-power-draw component of the device (e.g., a haptic engine, a high-brightness backlight mode, or an RF power amplifier). The inspection trace is designed to be slightly more brittle or exposed than the fuse trace. When a significant physical shock occurs, the inspection trace breaks first, which is detected by the power management IC (PMIC). The PMIC then intentionally blows the adjacent fuse trace by shunting a high current through it. This permanently disables the non-essential component, reducing overall power consumption and thermal load, thus preserving battery life and the functionality of core components (CPU, memory, main display) in a damaged device.

• Mermaid Diagram:

  stateDiagram-v2
      state Full_Functionality {
          direction LR
          Haptics_On
          Backlight_High
      }
      state Degraded_Mode {
          direction LR
          Haptics_Off
          Backlight_Low
      }
      Full_Functionality --> Degraded_Mode: Shock Event
      Shock_Event: Inspection trace breaks.
      Shock_Event: PMIC detects break.
      Shock_Event: PMIC blows haptics fuse.
  

---

Combination Prior Art Scenarios

Scenario 1: Integration with VESA Display Stream Compression (DSC) Standard

• Enabling Description: The status of the inspection interconnect (fourth signal interconnect) on a display panel is encoded into unused bits of the VESA DSC bitstream. The DSC standard allows for visually lossless compression of video data sent to a display panel. The display driver IC or TCON (Timing Controller) that receives the compressed stream reads the continuity of the inspection trace. It then embeds this 1-bit (OK/FAIL) status into the compressed video data frames being sent to the source GPU. The graphics driver on the host system can then decode this status and log it, flag a hardware error in the operating system, or trigger a diagnostic routine, without requiring any dedicated hardware lines back from the display panel. This provides a software-level health monitoring channel over the existing video data interface.

Scenario 2: Integration with MIPI DSI-2 (Display Serial Interface) Standard

• Enabling Description: The MIPI DSI-2 specification includes a bi-directional bus mode for communication from the peripheral (display) back to the host. The inspection interconnect's state (pass/fail, or even analog resistance values from a piezoresistive trace) is read by the display's driver IC. This status is then formatted as a standardized Generic Read Response packet. The host processor can periodically issue a Generic Read Request command over the DSI-2 bus to poll the display for its structural integrity status. This check can be integrated into the device's boot-up sequence or run as a periodic background health check, leveraging the existing high-speed display interface for diagnostics.

Scenario 3: Integration with Android Open Source Project (AOSP) Hardware Abstraction Layer (HAL)

• Enabling Description: A new HAL module, IIntegrity.hal, is defined within AOSP. This HAL provides a standardized interface for the Android framework to query the structural integrity of hardware components. For a device implementing the '762 patent's invention, the device-specific HAL implementation communicates with the touch controller or display driver (via I2C, SPI, or MIPI DSI-2 as in Scenario 2) to read the status of the inspection interconnect. Android applications with the appropriate permissions could then call an API, e.g., HardwareManager.getSubstrateStatus(), to check if the screen has been physically compromised. This information could be used by warranty service apps, device diagnostic tools, or high-security applications to verify the physical tamper-status of the device.