Prior art

Analysis of Prior Art for U.S. Patent 8,704,762

As of the current date, May 13, 2026, the following analysis details the most relevant prior art cited against U.S. Patent 8,704,762, titled "Display device." The analysis focuses on the potential for anticipation of the patent's claims under 35 U.S.C. § 102, which pertains to novelty.

The core invention of US Patent 8,704,762 lies in a display device, which includes a coordinate input device (touch panel) or a display panel, featuring a dedicated signal interconnect placed along the periphery of the substrate. This "second" or "fourth" signal interconnect is designed to surround the primary functional areas (the detection region and its associated "first" signal interconnects). Its purpose is to serve as a diagnostic line; by checking its electrical continuity between two dedicated inspection terminals, one can easily detect physical defects like chipping or cracks at the substrate's edge, which might otherwise be difficult to observe visually after assembly.

Below are the most pertinent prior art references cited during the patent's prosecution and their relevance to the claims.

1. JP 2002-350896 A (Assigned to NEC Corp)

• Full Citation: Japanese Patent Application Publication No. JP 2002-350896 A.
• Publication Date: December 6, 2002.
• Filing Date: May 24, 2001.
• Brief Description: This reference discloses a liquid crystal display (LCD) device with a method for detecting disconnection in common interconnects. It describes connecting common interconnects, which are arranged in parallel, to each other at the peripheral edge portion of the display screen. The design includes an opening at a central portion to facilitate the detection of disconnections in these common lines using an array testing technique.
• Potential Anticipation of Claim(s): This reference was considered by the applicant and is mentioned in the background section of US 8,704,762 (Col. 2, lines 8-15). While it relates to detecting interconnect defects, it does not appear to anticipate the key elements of the independent claims of the '762 patent.
  • Claim 1 of US 8,704,762 requires a separate "second signal interconnect" disposed outside the "first signal interconnect" near the peripheral edge, specifically for inspection of substrate integrity (chipping/cracking). JP 2002-350896 describes a method of testing the functional common interconnects themselves by linking them at the periphery. It does not teach a distinct, surrounding, non-functional line dedicated solely to physical defect inspection. The '762 patent explicitly distinguishes its invention by stating that the method in JP '896 "requires inspection on every signal interconnect, it may take extremely much time" (Col. 2, lines 36-38), whereas its own invention provides a simple pass/fail test for the substrate edge.

2. US 2009/0284483 A1 (Lee et al.)

• Full Citation: U.S. Patent Application Publication No. 2009/0284483 A1, Inventors: Lee, et al., Assignee: LG Display Co., Ltd.
• Publication Date: November 19, 2009.
• Filing Date: May 14, 2008.
• Brief Description: Lee et al. describe a touch screen panel integrated with an LCD. The disclosure includes details on the routing of signal lines and electrodes. It addresses the need for testing and inspection during manufacturing. Specifically, it discloses test lines and pads for evaluating the electrical characteristics of the touch sensor electrodes and their connections.
• Potential Anticipation of Claim(s): This reference is highly relevant as it discusses testing structures within a touch-enabled display.
  • Claim 1 and dependent claims: Lee et al. disclose various test lines and circuits. However, the primary purpose of the test lines described appears to be for checking the electrical properties (shorts, opens) of the functional touch sensor lines (e.g., the Rx and Tx electrodes) rather than a dedicated, peripheral "guard ring" style interconnect for detecting physical substrate damage. The novelty of claim 1 of the '762 patent rests on the specific structural arrangement and purpose of the second signal interconnect: being located outside the functional signal lines, near the peripheral edge, surrounding the functional area, and being used to detect physical chipping or cracking. A detailed review of Lee et al.'s figures and description would be necessary to confirm if it discloses this exact structure and purpose. If its test lines are intermingled with or are part of the functional interconnects, it would not anticipate the claimed invention.

3. JP 11-149097 A (Assigned to Fujitsu Ltd)

• Full Citation: Japanese Patent Application Publication No. JP H11-149097 A.
• Publication Date: June 2, 1999.
• Filing Date: November 21, 1997.
• Brief Description: This patent application discloses a plasma display panel (PDP) that includes a test pattern of wiring on the substrate. The test wiring is designed to check for breaks or short circuits in the signal lines. The test pattern is placed in the non-display area of the panel and can be used to identify manufacturing defects.
• Potential Anticipation of Claim(s): Similar to the other references, this document addresses the problem of defect detection using dedicated test lines.
  • Claims 1 and 2: The key question for anticipation is whether the "test pattern of wiring" in JP 11-149097 A is structurally and functionally equivalent to the "second signal interconnect" and "fourth signal interconnect" of the '762 patent. Claim 1 specifies that the interconnect is "disposed outside the first signal interconnect but near the peripheral edge of the transparent substrate" and that it "surround[s] the area where the detection region is included and the first signal interconnect is formed." If the test wiring in JP '097 is arranged in this specific peripheral, surrounding manner for the purpose of detecting edge defects that could sever the line, it could be considered to anticipate the claim. However, test lines are often designed to check for shorts between adjacent functional lines or opens within them, and may not necessarily form a continuous loop around the periphery as taught by the '762 patent for detecting physical substrate damage.

Summary

The novelty of US Patent 8,704,762 hinges on a specific, elegant solution: a single, continuous conductive loop placed at the outermost edge of the substrate, outside of all functional wiring, whose sole purpose is to act as a tripwire for physical damage. While prior art, including JP 2002-350896, US 2009/0284483 A1, and JP 11-149097 A, discloses various forms of test lines and interconnects for diagnosing electrical faults in display and touch panels, none appear to explicitly teach the precise structure and purpose claimed in the '762 patent. The prior art focuses on testing the integrity of the functional circuits, whereas the '762 patent provides a method for testing the integrity of the substrate itself, thereby indirectly confirming that the functional circuits, which lie inward from the inspection line, are likely undamaged by edge chipping or cracks. Therefore, direct anticipation under 35 U.S.C. § 102 by these references is unlikely, as they do not appear to disclose all elements of the independent claims arranged as specified.