Obviousness

Based on my analysis of the prior art cited on the face of US patent 8,704,762 and other analogous art, the independent claims of the '762 patent would likely be rendered obvious under 35 U.S.C. § 103. The core invention—an additional, dedicated conductive line at the periphery of a substrate for detecting cracks or chips—is a combination of a standard display/touch panel structure with a known testing technique from the broader field of electronics manufacturing.

A person having ordinary skill in the art (PHOSITA) in display and touch panel design circa 2010-2011 would have been familiar with the problem of substrate chipping during manufacturing and handling, which could sever critical signal interconnects. The motivation to find a simple, low-cost method for detecting such damage before final assembly would have been high.

Obviousness Analysis of Independent Claim 1

Claim 1 describes a display device with a coordinate input device (touch panel) that includes a second signal interconnect acting as a dedicated inspection line for detecting substrate damage.

An obviousness rejection of Claim 1 can be formulated based on the combination of a primary reference teaching the general structure of a touch panel and a secondary reference teaching the use of a peripheral crack-detection line.

• Primary Reference: A reference like US 2008/0150912 A1 (Hotelling et al.), which is representative of the state of the art for capacitive touch panels around the priority date of the '762 patent. Hotelling describes the fundamental structure claimed in the '762 patent, including a transparent substrate with detection electrodes, and signal interconnects (first signal interconnect) routed in the border regions outside the active detection area to connect to a flexible interconnect substrate.
• Secondary Reference: US 6,249,124 B1 (Tumey et al.) teaches a method for testing for cracks in the ceramic substrate of an electronic device. Tumey explicitly discloses forming a conductive trace (a "crack detection line") along the perimeter of the substrate. This line is connected to its own test pads. The principle is that a crack in the substrate will sever the line, creating a detectable open circuit.

Combination and Motivation

A PHOSITA, starting with the touch panel design of Hotelling, would be aware of the problem articulated in the '762 patent's own background section: "If chipping or crack is formed at the end of the glass substrate at the cutting step or during handling... a problem with interconnect defect arises" (Column 1, lines 30-34). This was a well-known manufacturing yield issue.

The PHOSITA would be motivated to find a reliable method to screen for such defects. The solution taught by Tumey—using a sacrificial trace along the substrate edge—is a direct and analogous solution to this exact problem, albeit in the context of a ceramic IC substrate rather than a glass display substrate. The motivation to combine would be to apply the known testing methodology of Tumey to the known touch panel structure of Hotelling to solve the known problem of detecting peripheral damage.

The implementation would be straightforward:

1. On the same layer as Hotelling's first signal interconnect, a designer would add another trace, the second signal interconnect, following the teaching of Tumey.
2. This new trace would be placed outside the functional first signal interconnect but near the edge of the substrate, as this is the most effective location to detect peripheral chips and cracks, precisely as Tumey teaches.
3. This trace would be connected to its own dedicated "electrode terminals for inspection," again as taught by Tumey, to allow for a simple continuity test (e.g., a resistance measurement).

This combination directly arrives at the invention of Claim 1. There would be a reasonable expectation of success, as forming conductive traces on glass is a fundamental process in display manufacturing.

Obviousness Analysis of Independent Claim 9

Claim 9 describes a display panel (rather than a touch panel) with a fourth signal interconnect serving as a dedicated inspection line. The logic is identical to the analysis for Claim 1.

An obviousness rejection of Claim 9 can be formulated based on the combination of a reference teaching a standard display panel structure and Tumey.

• Primary Reference: A reference such as JP-A-2002-350896 (Abe), cited by the '762 patent, or the general description of an active-matrix LCD panel provided in the '762 patent's background. These references teach a substrate with video and scanning signal lines, a display area, and signal interconnects (third signal interconnect) in the peripheral region connecting to driver circuitry.
• Secondary Reference: US 6,249,124 B1 (Tumey et al.), as described above.

Combination and Motivation

The motivation to combine these references is the same as for Claim 1. The substrate of a display panel is just as susceptible to chipping and cracking during manufacturing as the substrate of a touch panel. The consequences of an undetected crack severing a third signal interconnect (controlling entire rows or columns of pixels) are significant.

A PHOSITA designing the display panel taught by a reference like Abe would be motivated by the same need for improved defect detection. Applying the crack-detection methodology from Tumey to the display panel substrate would be a simple and obvious step to improve manufacturing yield and reliability. The designer would add a fourth signal interconnect along the periphery, outside the functional third signal interconnect, with dedicated test terminals. This would allow for a quick electrical test to confirm the physical integrity of the substrate's edge before the costly process of bonding driver chips and final assembly.

This combination of a standard display panel layout with the testing principle from Tumey would render the structure described in Claim 9 obvious to a person of ordinary skill in the art.