Derivative works — US Patent 8704762

Defensive Disclosure and Prior Art Generation for US 8,704,762

Document ID: DD-8704762-20260513
Publication Date: 2026-05-13
Subject Matter: Derivative works and improvements upon the inspection interconnect for display devices as described in US Patent 8,704,762.

Derivatives Based on Claim 1: Coordinate Input Device Inspection Interconnect

Axis 1: Material & Component Substitution

Derivative 1.1: Piezoresistive Polymer Inspection Trace

Enabling Description: The second signal interconnect is fabricated from a piezoresistive polymer composite, such as carbon-black-infused polydimethylsiloxane (PDMS) or a poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) formulation. Unlike a simple conductive trace which only detects binary open/closed circuits (continuity), this material changes its electrical resistance in response to mechanical stress. The inspection terminals are connected to a high-precision digital multimeter or an ADC-equipped microcontroller. During quality control or device operation, a baseline resistance is measured. A micro-crack or delamination near the substrate edge, even if it does not fully sever the trace, will induce localized strain, causing a measurable change in resistance. This allows for pre-failure detection and characterization of the severity of the defect, rather than a simple go/no-go test. The trace can be screen-printed or inkjet-printed onto the substrate (e.g., third substrate SUB3) in the same process step as other organic electronic components.

Mermaid Diagram:

graph TD
    subgraph Piezoresistive Inspection Circuit
        A(Inspection Terminal 1) -->|Baseline R = 10kΩ| B{Piezoresistive Polymer Trace};
        B --> C(Inspection Terminal 2);
        D[Microcontroller with ADC] -- Reads Resistance --> B;
        E{Micro-crack introduces strain} -.-> B;
        B -- Resistance changes to 10.5kΩ --> D;
        D -- Reports Anomaly --> F[System Controller];
    end

Derivative 1.2: Embedded Fiber-Optic Loop for Strain and Fracture Detection

Enabling Description: The second signal interconnect is replaced with a single-mode optical fiber loop embedded or bonded along the periphery of the transparent substrate. One end of the loop is coupled to a light source (e.g., a VCSEL at 850nm), and the other end is coupled to a photodetector. A Fiber Bragg Grating (FBG) is inscribed into the fiber at one or more points along its path. The inspection circuit monitors two parameters:
1. Light Transmission: A complete fracture of the substrate will sever the fiber, causing a total loss of signal at the photodetector, providing a clear indication of catastrophic failure.
2. Bragg Wavelength Shift: Mechanical stress or thermal expansion/contraction of the substrate will strain the FBG, causing a shift in the reflected Bragg wavelength (ΔλB). This shift is monitored by a wavelength interrogator. This provides a highly sensitive, non-electrical method for detecting stress concentration points that precede fracture, making it suitable for high-reliability applications and environments with high EMI.

Mermaid Diagram:

sequenceDiagram
    participant VCSEL as Light Source (850nm)
    participant Loop as Fiber-Optic Loop with FBG
    participant Interrogator as FBG Interrogator
    participant Photodetector
    participant System

    VCSEL->>Loop: Emits Continuous Light
    Loop->>Photodetector: Transmits Light
    activate Photodetector
    Interrogator->>Loop: Monitors Reflected Wavelength (λB)
    activate Interrogator
    System->>System: Baseline: No Stress
    Note over Loop: Substrate bends, creating strain
    Loop-->>Interrogator: Reflected Wavelength Shifts (ΔλB)
    Interrogator-->>System: Reports Strain Anomaly
    Note over Loop: Substrate cracks, severing fiber
    Loop--xPhotodetector: Light transmission ceases
    Photodetector-->>System: Reports Catastrophic Failure

Axis 2: Operational Parameter Expansion

Derivative 2.1: Cryogenic Flexible Display Integrity Monitoring

Enabling Description: The invention is applied to a flexible polyimide substrate-based OLED display designed for operation in cryogenic environments (-150°C to -200°C), such as in deep-space instrumentation or superconducting quantum computer interfaces. At these temperatures, material embrittlement is a primary failure mode. The inspection interconnect (second signal interconnect) is a multi-trace structure composed of materials with differing coefficients of thermal expansion (CTE), for example, parallel traces of gold (Au) and constantan. As the device is cooled, the differential strain between the traces and the substrate induces a measurable change in the resistance ratio between the two traces. An anomalous reading indicates non-uniform thermal contraction or material fatigue, predicting a potential fracture upon further thermal cycling. The inspection is performed by a four-wire Kelvin sensing method to eliminate contact resistance effects, which can be significant at low temperatures.

Mermaid Diagram:

stateDiagram-v2
    [*] --> Unstressed_293K
    Unstressed_293K: R_Au / R_Const = X
    Unstressed_293K --> Cooling
    Cooling --> Stressed_77K: Uniform Contraction
    Stressed_77K: R_Au / R_Const = Y
    Stressed_77K --> Unstressed_293K: Warming
    Cooling --> Anomaly_Detected: Non-uniform stress
    Anomaly_Detected: R_Au / R_Const ≠ Y
    Anomaly_Detected --> Failure_Risk_Flagged
    Failure_Risk_Flagged --> [*]

Derivative 2.2: High-Frequency Impedance Monitoring of Inspection Trace

Enabling Description: Instead of a DC continuity or resistance check, the inspection interconnect is treated as a transmission line. An AC signal in the RF range (e.g., 100 MHz - 1 GHz) is injected into one inspection terminal, and the S-parameters (S11 - return loss, S21 - insertion loss) are measured at the terminals using a vector network analyzer (VNA) circuit integrated into the display driver IC. A micro-crack, even if it doesn't break the DC path, creates a capacitive or inductive discontinuity. This discontinuity causes an impedance mismatch, which is detectable as a significant change in the S-parameters at specific frequencies. Time-Domain Reflectometry (TDR) can be implemented by injecting a fast-rise-time pulse and analyzing the reflection. The timing and shape of the reflection can precisely locate the physical position of the defect along the peripheral trace.

Mermaid Diagram:

flowchart LR
    subgraph Test Setup
        A[Signal Generator (100MHz)] --> B(Inspection Terminal 1)
        C(Inspection Terminal 2) --> D[RF Detector/ADC]
    end
    subgraph Substrate
        B --> E{Peripheral Inspection Trace};
        E --> C;
        F(Micro-crack) -- Creates Impedance Mismatch --> E;
    end
    D -- Measures S21 parameter --> G{Analysis Unit};
    G -- Compares to Golden Sample Profile --> H{Pass/Fail/Locate};

Axis 3: Cross-Domain Application

Derivative 3.1: Aerospace - Smart Skin for Micrometeoroid Impact Detection

Enabling Description: The display device substrate is replaced with the composite skin panel of a satellite or spacecraft. A grid of peripheral and internal inspection interconnects, analogous to the second signal interconnect, is printed or embedded in a non-conductive layer of the skin. The interconnects are made from a brittle, conductive material. A micrometeoroid or orbital debris (MMOD) impact creates a shockwave that fractures the brittle traces in a localized area. By continuously monitoring the continuity of the grid segments, the system can detect an impact, estimate its location by identifying which traces were severed, and infer the impact energy by the number of fractured traces. This provides real-time structural health monitoring without complex acoustic sensors.

Mermaid Diagram:

graph TD
    subgraph Satellite Skin Panel
        direction LR
        A1--Trace Y1---A2
        B1--Trace Y2---B2
        C1--Trace Y3---C2

        subgraph Perpendicular Traces
            direction TB
            D1--Trace X1---D2
            E1--Trace X2---E2
            F1--Trace X3---F2
        end
    end
    G(MMOD Impact) -- fractures traces --> X2 & Y2
    H[Continuity Monitor] -- detects open circuits on --> I(X2 & Y2 terminals)
    I --> J[Onboard Computer]
    J -- Triangulates Location --> K(Report: Impact at coordinates X2, Y2)

Derivative 3.2: AgTech - Smart Greenhouse Panel Integrity System

Enabling Description: The concept is applied to large polycarbonate or glass panels used in advanced agricultural greenhouses. The inspection interconnect is a transparent conductive oxide (e.g., ITO, FTO) trace deposited around the perimeter of each panel. These panels are subject to stress from wind, hail, and thermal expansion. A break in a panel, which could compromise the controlled internal environment, severs the trace. Each panel's trace is connected to a central monitoring system via a low-power wireless mesh network (e.g., LoRaWAN). When a break occurs, the panel's node sends an alert with its unique ID, allowing for immediate identification and replacement of the damaged panel, minimizing crop loss.

Mermaid Diagram:

classDiagram
class GreenhouseController {
    +monitorPanels()
    +receiveAlert(panelID)
}
class PanelNode {
    <<LoRaWAN>>
    -panelID: string
    -traceContinuity: boolean
    +checkIntegrity()
    +sendAlert()
}
class InspectionTrace {
    -isBroken: boolean
}
GreenhouseController "1" -- "*" PanelNode : Manages
PanelNode "1" -- "1" InspectionTrace : Monitors

Derivative 3.3: Medical - Implantable Device Hermetic Seal Verification

Enabling Description: The substrate is the ceramic or titanium casing of an implantable medical device, such as a pacemaker or neurostimulator. The inspection interconnect is a thin-film trace deposited around the hermetic seal joint between the casing halves. The trace runs both on the exterior and interior, connected by a sealed via. After sealing (e.g., by laser welding), the continuity of this trace is verified to confirm the integrity of the weld. Post-implantation, the device can periodically perform a self-check. The ingress of bodily fluids into a compromised seal would corrode and break the trace, providing an early warning of seal failure before moisture damages the critical internal electronics.

Mermaid Diagram:

graph TD
    A(Pacemaker Electronics) -- runs periodic check --> B{Trace Terminals}
    subgraph Device Casing
        C(External Trace) -- via --> D(Internal Trace)
        B -- connected to --> C & D
    end
    E(Seal Breach) -- fluid ingress --> F(Corrosion)
    F -- severs trace --> C
    A -- detects open circuit --> G(Transmit Failure Alert to External Monitor)

Axis 4: Integration with Emerging Tech

Derivative 4.1: IoT-Enabled Self-Reporting Display for Supply Chain

Enabling Description: The inspection interconnect terminals of the touch panel (or display panel) are connected to an ultra-low-power microcontroller with an integrated NFC (Near Field Communication) or BLE (Bluetooth Low Energy) module. This unit is powered by an energy-harvesting circuit or a small thin-film battery. Throughout the supply chain—from the panel fabrication plant to the OEM assembly line—the integrity of the panel's substrate can be checked wirelessly at each handoff point by simply tapping it with an NFC reader or scanning for its BLE beacon. A detected open circuit (indicating a crack from mishandling) is immediately logged to a cloud database, pinpointing the stage where the damage occurred.

Mermaid Diagram:

sequenceDiagram
    participant Fab as Panel Fab
    participant Logistics as Shipping
    participant OEM
    participant Cloud
    Fab->>Logistics: Ship Panel (Integrity OK)
    Logistics->>Logistics: Panel is dropped (Crack occurs)
    OEM->>Logistics: Receives Panel
    OEM->>OEM: Scans Panel with NFC Reader
    Note over OEM: Reader detects open circuit
    OEM->>Cloud: Logs Damaged Panel ID & Timestamp
    Cloud-->>Fab: Notifies of Damage in Transit

Derivative 4.2: AI-Driven Predictive Failure Analysis

Enabling Description: A display device incorporates an array of multiple, parallel inspection interconnects along the periphery, each made of slightly different materials or having different geometries (e.g., varying thickness, serpentine vs. straight). This creates a sensor array that responds differently to stress, temperature, and humidity. An onboard AI/ML model, trained on a dataset of previously failed units, continuously monitors the resistance, capacitance, and thermal drift of all traces in the array. The model recognizes subtle, multi-variate patterns in the data that are precursors to specific failure modes (e.g., corner crack vs. side delamination). The device can then provide a predictive warning to the user, e.g., "Structural stress detected. Avoid flexing device. Backup data now," long before the damage becomes critical.

Mermaid Diagram:

flowchart TD
    subgraph Sensor Array
        A[Trace 1 (Au)]
        B[Trace 2 (Ag)]
        C[Trace 3 (ITO)]
    end
    D[Multiplexer & ADC] --> E[Feature Vector (R1, C1, R2, C2, ...)]
    E --> F(Onboard ML Model)
    F -- Pattern Recognition --> G{Failure Mode Prediction}
    G --> H(Corner Crack - 85% Confidence)
    H --> I[User Alert System]

Axis 5: The "Inverse" or Failure Mode

Derivative 5.1: Fused-Trace for Graceful Degradation

Enabling Description: The inspection interconnect is designed not just to detect failure, but to trigger a safe-fail mode. It is co-located with a "fuse" trace that controls power to a non-essential but high-power-draw component of the device (e.g., a haptic engine, a high-brightness backlight mode, or an RF power amplifier). The inspection trace is designed to be slightly more brittle or exposed than the fuse trace. When a significant physical shock occurs, the inspection trace breaks first, which is detected by the power management IC (PMIC). The PMIC then intentionally blows the adjacent fuse trace by shunting a high current through it. This permanently disables the non-essential component, reducing overall power consumption and thermal load, thus preserving battery life and the functionality of core components (CPU, memory, main display) in a damaged device.

Mermaid Diagram:

stateDiagram-v2
    state Full_Functionality {
        direction LR
        Haptics_On
        Backlight_High
    }
    state Degraded_Mode {
        direction LR
        Haptics_Off
        Backlight_Low
    }
    Full_Functionality --> Degraded_Mode: Shock Event
    Shock_Event: Inspection trace breaks.
    Shock_Event: PMIC detects break.
    Shock_Event: PMIC blows haptics fuse.

Combination Prior Art Scenarios

Scenario 1: Integration with VESA Display Stream Compression (DSC) Standard

Enabling Description: The status of the inspection interconnect (fourth signal interconnect) on a display panel is encoded into unused bits of the VESA DSC bitstream. The DSC standard allows for visually lossless compression of video data sent to a display panel. The display driver IC or TCON (Timing Controller) that receives the compressed stream reads the continuity of the inspection trace. It then embeds this 1-bit (OK/FAIL) status into the compressed video data frames being sent to the source GPU. The graphics driver on the host system can then decode this status and log it, flag a hardware error in the operating system, or trigger a diagnostic routine, without requiring any dedicated hardware lines back from the display panel. This provides a software-level health monitoring channel over the existing video data interface.

Scenario 2: Integration with MIPI DSI-2 (Display Serial Interface) Standard

Enabling Description: The MIPI DSI-2 specification includes a bi-directional bus mode for communication from the peripheral (display) back to the host. The inspection interconnect's state (pass/fail, or even analog resistance values from a piezoresistive trace) is read by the display's driver IC. This status is then formatted as a standardized Generic Read Response packet. The host processor can periodically issue a Generic Read Request command over the DSI-2 bus to poll the display for its structural integrity status. This check can be integrated into the device's boot-up sequence or run as a periodic background health check, leveraging the existing high-speed display interface for diagnostics.

Scenario 3: Integration with Android Open Source Project (AOSP) Hardware Abstraction Layer (HAL)

Enabling Description: A new HAL module, IIntegrity.hal, is defined within AOSP. This HAL provides a standardized interface for the Android framework to query the structural integrity of hardware components. For a device implementing the '762 patent's invention, the device-specific HAL implementation communicates with the touch controller or display driver (via I2C, SPI, or MIPI DSI-2 as in Scenario 2) to read the status of the inspection interconnect. Android applications with the appropriate permissions could then call an API, e.g., HardwareManager.getSubstrateStatus(), to check if the screen has been physically compromised. This information could be used by warranty service apps, device diagnostic tools, or high-security applications to verify the physical tamper-status of the device.