Invalidity dossier
US 8605480
Read only memory device with complemenary bit line pair
Current assignee: STMicroelectronics International NV
Added 9/21/2026, 9:30:37 AM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US8605480B2
Title: "Read only memory device with complemenary bit line pair" (spelling as listed in the source).
Patent number / application: US8605480B2; application US13/178,856; earlier publication US20120163064A1.
Inventors: Nitin Jain and Piyush Jain. Original assignee: STMicroelectronics International NV (assignment records in the source also list STMicroelectronics Pvt Ltd.). Priority date: 2010-12-28. Filing date: 2011-07-08. Grant/publication date: 2013-12-10. Legal status: Expired – Fee Related, with an adjusted expiration listed as 2031-12-10 (source states status is an assumption, not a legal conclusion).
Field and purpose: The invention relates to read only memory (ROM) devices, including ROM in integrated circuits. The source explains that conventional ROM arrays use a single bit line per bit, which may require an unbalanced sense amplifier needing high offset and suffering speed and dynamic power penalties, plus high static power loss from core-array leakage and sensitivity to process, voltage and temperature variation. The described approach instead associates a pair of bit lines with each memory cell to form a complementary output.
Plain-language scope (from the excerpt): A ROM cell circuit comprises at least one memory cell and a pair of bit lines per cell forming a complementary output, with the cell coupled to the first or second bit line to represent a stored bit value. Cells may use NMOS transistors (gate to a word line, drain to the first or second bit line, source to a low reference or an associated memory cell multiplex line) or PMOS equivalents (source to a high reference or multiplex line). The excerpt also describes memory slice circuits and ROM circuits chaining cells/slices with switches feeding sense-amplifier inputs, and a method of associating the complementary bit-line pair and coupling each cell to a first or second bit line.
Source: https://patents.google.com/patent/[US8605480](/patent/US8605480)/en
What the excerpt does not establish: The full claim set, dependent-claim details, the complete specification, drawing contents, and any description of prior-art documents are not fully reproduced. No litigation, ownership-transfer, validity, or prior-art conclusions are drawn here.
Generated 10/1/2026, 10:02:18 PM
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Litigation summary
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Proceedings on file (0)
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PTAB challenges
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Assignment history
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Prior art
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Obviousness
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Extensions
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Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.