US 8593888

Summary of U.S. Patent 8,593,888: A Novel Approach to Semiconductor Memory

Washington D.C. - A detailed analysis of United States Patent 8,593,888, titled "Semiconductor memory device," reveals a focused invention on improving the efficiency and reducing the size of memory chip circuitry. The patent, issued on November 26, 2013, has seen a transfer of ownership, with the current assignee being Advanced Memory Technologies LLC.

Key Patent Information:

• Title: Semiconductor memory device
• Assignee: Advanced Memory Technologies LLC (as of April 22, 2024)
• Inventors: Reiji Mochida, Takafumi Maruyama, Yukimasa Hamamoto
• Filing Date: August 22, 2012
• Issue Date: November 26, 2013
• Abstract: The patent describes a semiconductor memory device where a single voltage regulator is used for two different functions by employing a set of switches. In one mode of operation, the regulator's output controls the drain voltage of a memory cell. In a second mode, it controls the gate voltage of the same memory cell. This design aims to reduce the circuit area by eliminating the need for a second regulator.

Plain-Language Overview of Independent Claims

The independent claims of a patent define the core of the invention in the broadest terms.

Independent Claim 1: This claim outlines a semiconductor memory device that can be erased and have new data written to it using electrical signals. The key components of this invention are a memory cell, a single voltage regulator, a pair of switches (first and second), and a "voltage applying transistor" which, as its name suggests, applies a voltage to the memory cell. The invention lies in how these components are connected: the output of the single regulator is fed into both switches. The first switch then controls the gate of the voltage applying transistor (which in turn affects the memory cell's drain), while the second switch directly controls the voltage going to the gate of the memory cell itself. This clever wiring allows one regulator to do the job of two.

Independent Claim 2: This claim presents an alternative design for a similar semiconductor memory device. It also uses a single regulator, a memory cell, and a voltage applying transistor. However, the connections are slightly different. Here, the regulator's output is directly connected to the gate of the voltage applying transistor and also to the input of a second switch. A third switch is then placed in the path between the voltage applying transistor and the drain of the memory cell. The second switch's output, as in the first claim, is connected to the gate of the memory cell. This represents a different circuit architecture to achieve the same space-saving goal of using only one regulator.

At present, no litigation in the U.S. Court of Appeals for the Federal Circuit (CAFC) dockets for 2026 involving US Patent 8,593,888 has been identified. However, the patent landscape is dynamic, and the status of this patent could change.