Prior art

To identify the most relevant prior art for US patent 8593888, I will examine the patent citations listed within the patent itself.

Most Relevant Prior Art for US Patent 8,593,888

The US patent 8,593,888 cites the following patent documents as prior art:

1. JP2008217914A

   • Full Citation: JP2008217914A, Toshiba Corp, "Nonvolatile semiconductor memory device", published 2008-09-18.
   • Publication/Filing Date: The publication date is September 18, 2008. The priority date is March 6, 2007.
   • Brief Description: This patent describes a nonvolatile semiconductor memory device. The background section of US8593888B2 mentions that a technique where the output of a first regulator is coupled to the gate of a memory cell, and the output of a second regulator is coupled to the gate of a voltage applying transistor, is described in Japanese Patent Publication No. 2008-217914 (FIG. 9).
   • Potentially Anticipates Claim(s) under 35 U.S.C. § 102: JP2008217914A, as described in the background of US8593888B2, utilizes two separate regulators for controlling the gate voltage of the memory cell and the gate of the voltage applying transistor. This directly contrasts with the core innovation of US8593888B2, which aims to combine these functions into a single regulator to reduce circuit area. Therefore, JP2008217914A potentially anticipates the broader concept of controlling both the memory cell gate and the voltage applying transistor gate in a semiconductor memory device, but not the specific improvement of using only one regulator for both functions, which is central to claims 1 and 2 of US8593888B2.

2. US7428170B2

   • Full Citation: US7428170B2, [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.), "Voltage generation circuit, flash memory device including the same and method for programming the flash memory device", published 2008-09-23.
   • Publication/Filing Date: The publication date is September 23, 2008. The priority date is October 12, 2006.
   • Brief Description: This patent generally relates to voltage generation circuits and flash memory devices. Further details regarding its specific circuitry for regulating voltages to memory cell gates and drain applying transistors would require a deeper dive into the full text of US7428170B2.
   • Potentially Anticipates Claim(s) under 35 U.S.C. § 102: Without a specific description of the voltage regulation scheme within US7428170B2 that directly aligns with or differs from the single-regulator approach of US8593888B2, it is difficult to definitively state which claims it might anticipate. If US7428170B2 discloses a system using multiple regulators for drain and gate voltages in a similar context to that described as conventional in US8593888B2's background, it could be considered relevant prior art for the general function but not for the area-saving innovation. If it, however, discloses a single regulator performing both functions, it could potentially anticipate claims 1 and 2.