Obviousness

Obviousness Analysis of US Patent 8,593,888 Under 35 U.S.C. § 103

This analysis evaluates the obviousness of US Patent 8,593,888 (the '888 patent) by considering combinations of prior art references that could render its claims obvious to a person having ordinary skill in the art (POSITA). The core inventive concept of the '888 patent is to reduce circuit area in semiconductor memory devices by utilizing a single voltage regulator for multiple functions—specifically, controlling the drain voltage of a memory cell via a voltage applying transistor during one operation mode (e.g., write) and controlling the gate voltage of the memory cell directly during another operation mode (e.g., read). The priority date for the '888 patent is March 10, 2010.

Identified Prior Art References (Published before March 10, 2010):

From the "Prior Art" and "Citations" sections, the following references are considered:

1. JP2008217914A (Published September 18, 2008, Toshiba Corp): Described in the '888 patent as conventional art, it teaches a semiconductor memory device where "the output of a first regulator is coupled to the gate of a memory cell, and also the output of a second regulator is coupled to the gate of a voltage applying transistor, so that the gate voltage of the memory cell is regulated while a voltage is applied from the drain terminal of the voltage applying transistor to the drain terminal of the memory cell."
2. US7428170B2 (Published September 23, 2008, [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.)): Titled "Voltage generation circuit, flash memory device including the same and method for programming the flash memory device."
3. US6456557B1 (Published September 24, 2002, Tower Semiconductor Ltd): Titled "Voltage regulator for memory device."
4. JP2008269727A (Published November 6, 2008, Matsushita Electric Ind Co Ltd): Titled "Boost circuit, semiconductor memory device, and driving method thereof."
5. JPH0512891A (Published January 22, 1993, Toshiba Corp): Titled "Semiconductor storage."
6. KR100368314B1 (Published January 24, 2003, Hynix Semiconductor Inc): Titled "Bias circuit of a flash memory."

Obviousness Combinations and Rationale

The '888 patent explicitly identifies the problem addressed by its invention: conventional circuits (like that described in JP2008217914A) require two regulators for different voltage regulation tasks, leading to increased circuit area. The '888 patent aims to overcome this by combining these functions into a single regulator.

A POSITA, skilled in the art of semiconductor memory design, would inherently be motivated to reduce circuit area and optimize resource utilization, as these are common design goals in the field.

Combination 1: JP2008217914A in view of US6456557B1 (or similar references teaching shared regulators)

• JP2008217914A teaches a nonvolatile memory device that includes:

  • Memory cells.
  • A voltage applying transistor to apply voltage to the drain terminal of the memory cell.
  • A first regulator coupled to the gate of the memory cell.
  • A second regulator coupled to the gate of the voltage applying transistor.
    This reference clearly sets forth the functional requirements for two distinct regulated voltages during different memory operations.

• US6456557B1 (Voltage regulator for memory device) is a relevant reference explicitly disclosing a voltage regulator for memory devices. While the full text is not provided, its title and general classification suggest it pertains to voltage regulation within memory. If US6456557B1 (or other similar prior art such as KR100368314B1 or JP2008269727A, which generally relate to voltage generation/bias in flash memories) teaches or suggests that a single voltage regulator can be designed with configurable or switchable outputs to provide different regulated voltages to different parts of a memory circuit at different times (e.g., during write versus read operations) to save circuit area, then the combination becomes apparent.

Motivation for Combination: A POSITA, reviewing JP2008217914A, would understand the need for regulated voltages for both the memory cell gate and the voltage applying transistor gate. Concurrently, a POSITA would be aware of the general industry pressure to reduce circuit area, as explicitly stated as a problem by the '888 patent itself. Upon encountering the disclosure in US6456557B1 (or similar art) regarding the efficient use of a single regulator with switchable outputs in a memory device, it would be an obvious design choice to adapt this "single regulator, multiple output" concept to the dual-regulator scheme of JP2008217914A. The motivation would be to achieve the known benefit of area reduction by replacing two separate regulators with a single, shared regulator whose output is selectively routed using switches, depending on the operational mode (write or read).

This combination would directly address the problem of "increasing the circuit area" caused by using two separate regulators, as highlighted by the '888 patent.

Addressing Independent Claim 1:

Claim 1 specifies: "one regulator, first and second switches... an output of the regulator is coupled to inputs of the first and second switches, an output of the first switch is coupled to a gate of the voltage applying transistor... and an output of the second switch is coupled to a gate of the memory cell."

If JP2008217914A teaches the necessity of a regulated voltage for the gate of the voltage applying transistor and for the gate of the memory cell, and a general voltage regulator patent like US6456557B1 teaches the use of a single regulator with multiple switched outputs to save area, a POSITA would find it obvious to apply the single-regulator-with-switches principle to the specific application in JP2008217914A. The first and second switches would serve to route the single regulator's output to either the voltage applying transistor's gate or the memory cell's gate, depending on the operational mode.

Addressing Independent Claim 2:

Claim 2 presents a slightly different configuration where the "output of the regulator is coupled to an input of the second switch and a gate of the voltage applying transistor" and a "third switch" is used to apply voltage from the voltage applying transistor to the memory cell drain.

This variation is also obvious in light of the same combination. A POSITA seeking to consolidate regulators would consider various switching arrangements to achieve the desired voltage applications. Coupling the regulator output directly to the voltage applying transistor's gate (as in claim 2) and using a separate switch (third switch) to control the path to the memory cell drain would be a straightforward design choice given the goal of sharing the regulator. The second switch would still connect the regulator to the memory cell gate.

Conclusion on Obviousness:

Given the clear problem statement in the '888 patent itself (reducing area by combining two regulators) and the presence of prior art teaching memory devices requiring multiple regulated voltages (JP2008217914A) alongside general knowledge or specific teachings of single, shared voltage regulators with switchable outputs for area efficiency in memory devices (e.g., US6456557B1), a POSITA would have been motivated to combine these elements. The combination would lead to the claimed invention by simply replacing the two discrete regulators of the prior art (JP2008217914A) with a single, multiplexed regulator whose output is routed by switches to perform the same functions at different times, thereby achieving the desired area reduction. The specific arrangements of switches in claims 1 and 2 represent conventional circuit design choices for routing signals based on operational modes.