Obviousness

Obviousness Analysis of US Patent 8587076 under 35 U.S.C. § 103

This analysis will identify combinations of prior art references that would render the independent claims of US Patent 8587076 obvious to a person having ordinary skill in the art (POSITA) at the time of the invention (priority date: 2005-08-05). A POSITA in this field would likely be a semiconductor device engineer or scientist with experience in MISFET design and fabrication, possessing a strong understanding of materials science and processing techniques for advanced CMOS technologies. Such a person would be aware of relevant prior art and capable of understanding and applying it in a routine manner or with ordinary skill, including fitting the teachings of multiple patents together like pieces of a puzzle.

Independent Device Claim 1 Overview:

This claim describes a semiconductor device featuring:

1. A high dielectric constant gate insulating film formed on an active region in a substrate.
2. A gate electrode formed on the high dielectric constant gate insulating film.
3. An insulating sidewall on each side of the gate electrode.
4. The high dielectric constant gate insulating film continuously extends from under the gate electrode to under the insulating sidewall.
5. The portion of this film under the sidewall has a smaller thickness than the portion under the gate electrode.

Combination 1: Ken Watanabe (2005) + General knowledge in the art

Prior Art Teaching:
The patent itself explicitly cites "Ken Watanabe, HfSiON - CMOS technology for achieving high performance and high reliability, Semi. Forum Japan, 2005" as describing known MISFET structures using a high dielectric constant gate insulating film. Specifically, FIGS. 16A and 16B of US8587076 illustrate known MISFETs, where a gate electrode 105 is formed on a well 102 (active region) with a high dielectric constant gate insulating film 104 interposed. An insulating sidewall 107 is formed on each side of the gate electrode 105. These figures also show extension regions 110 and pocket regions 111. The problem identified by the inventors is that in these known structures, the side end portions of the high dielectric constant gate insulating film are in direct contact with sidewalls, leading to degradation of dielectric constant and insulation property.

Motivation to Combine/Modify:
A POSITA, motivated to address the known degradation issues of high dielectric constant gate insulating films at the gate end portions when in direct contact with sidewalls, would seek ways to prevent this direct contact while maintaining the benefits of the high-k film. The patent states that the inventors devised a MISFET structure where the high dielectric constant gate insulating film is kept remaining under the sidewalls to prevent direct contact. However, a POSITA would also recognize the trade-off: keeping the full thickness of the high-k film under the sidewall increases gate/drain capacitance, impacting circuit speed, and complicates extension/LDD implantation due to the high-k film's thickness and heavy metal content (Reason 1 and 2 in the patent's summary).

Therefore, a POSITA would be motivated to modify the known structure (e.g., Watanabe's, as depicted in FIGS. 16A and 16B) by:

• Ensuring continuity: Maintaining the high dielectric constant gate insulating film continuously from under the gate electrode to under the sidewall to prevent direct contact and related degradation.
• Reducing thickness under sidewall: Intuitively, to mitigate the increased capacitance and implantation issues caused by the continuous high-k film under the sidewall, a POSITA would consider reducing the thickness of this portion. This would be a predictable variation using known techniques to achieve predictable results, as reducing dielectric thickness is a standard approach to control capacitance and facilitate implantation. The patent itself highlights that "the high dielectric constant gate insulating film is formed so as to have a smaller thickness in the part located under the sidewall than a thickness of the part located under gate electrode" to suppress capacitance increase and improve implantation.

Conclusion for Claim 1:
A POSITA, starting from the known MISFET structures (like those in Watanabe, illustrated in FIGS. 16A and 16B) and being aware of the challenges associated with high-k gate insulating films (degradation at sidewall contact, increased capacitance, and implantation difficulties), would find it obvious to modify the structure by:

1. Continuously extending the high dielectric constant gate insulating film from under the gate electrode to under the insulating sidewall to avoid direct contact with the sidewall.
2. Reducing the thickness of the high dielectric constant gate insulating film in the portion under the sidewall relative to the portion under the gate electrode, to mitigate parasitic capacitance and facilitate dopant implantation. This modification would be a logical and predictable design choice for a POSITA seeking to optimize performance and reliability in MISFETs using high-k gate dielectrics.

Independent Device Claim 2 Overview (describing a device with multiple sidewalls):

This claim describes a semiconductor device where:

1. The insulating sidewall includes a first insulating sidewall and a second insulating sidewall, with the first sidewall between the gate electrode and the second sidewall.
2. The high dielectric constant gate insulating film extends continuously from under the gate electrode to under the first insulating sidewall.
3. The part of this film under the first insulating sidewall is thinner than the part under the gate electrode.
   (Note: The patent summary presents several variations of this multi-sidewall configuration, which would typically be dependent claims or separate independent claims, each specifying different thickness relationships for the high dielectric constant gate insulating film under the various sidewalls).

Combination 2: Ken Watanabe (2005) (FIG. 16B) + T. Hori (1989) + H. Sayama et al. (2000) + General knowledge in the art

Prior Art Teaching:

• Ken Watanabe (2005): As discussed, this reference shows known MISFET structures with high dielectric constant gate insulating films. Specifically, FIG. 16B illustrates a structure with an insulating offset sidewall 106 interposed between the gate electrode 105 and the main sidewall 107. This structure is noted for optimizing the overlapping amount of the gate electrode and an extension region.
• T. Hori (1989), IEDM Tech. Dig., p. 777: This reference is cited in US8587076 for achieving a "high overlapping effect between a gate and a drain" which improves "device characteristics and hot carrier reliability". This suggests the importance of capacitive coupling between the gate electrode and the extension region.
• H. Sayama et al. (2000), IEDM Tech. Dig., p. 239: This reference describes a "double sidewall type MISFET in which an overlapping amount between a gate electrode and an extension region can be optimized in a simple manner". This directly addresses the concept of using multiple sidewalls (like a first and second insulating sidewall) to fine-tune device geometry.

Motivation to Combine/Modify:
A POSITA, starting with the understanding from Watanabe (FIG. 16B) that multiple sidewalls (e.g., offset and main sidewalls) are used to optimize gate-extension overlap, would be motivated to combine this with the knowledge from Hori regarding the benefits of strong capacitive coupling between the gate and extension region for performance and reliability.

The patent highlights the benefit of the high dielectric constant gate insulating film under the offset sidewall in making the capacitive coupling between the gate electrode and the n-type extension region stronger in the vicinity of the gate end, leading to a high overlapping effect and improved characteristics. However, just as with the single sidewall case, a POSITA would also recognize the drawbacks of a full-thickness high-k film under the offset sidewall (increased capacitance, implantation issues). The solution of reducing the thickness of the high-k film under the sidewall (as per the reasoning for independent claim 1) would also apply here.

Therefore, a POSITA, seeking to achieve the benefits of optimized gate-extension overlap using multiple sidewalls (as taught by Sayama et al. and exemplified in Watanabe's FIG. 16B) while simultaneously mitigating the disadvantages of a thick high-k film at the gate edges, would find it obvious to:

1. Implement a structure with a first insulating sidewall (offset sidewall) and a second insulating sidewall, following the principles of double sidewall MISFETs known in the art (Sayama et al., Watanabe FIG. 16B).
2. Continuously extend the high dielectric constant gate insulating film from under the gate electrode to under the first insulating sidewall, to maintain continuity and prevent degradation.
3. Reduce the thickness of the high dielectric constant gate insulating film in the portion located under the first insulating sidewall, compared to the thickness under the gate electrode. This modification would optimize the capacitive coupling for improved device characteristics and reliability (Hori) while suppressing parasitic capacitance and simplifying implantation, which are known challenges with high-k films.

Conclusion for Claim 2:
A POSITA, leveraging the teachings of Watanabe (FIG. 16B) for double sidewall structures, Sayama et al. for optimizing gate-extension overlap in such structures, and Hori for the benefits of gate-drain overlap, combined with the general understanding of high-k gate dielectric challenges, would find it obvious to create a device where:

• A first (offset) sidewall and a second sidewall are present.
• The high dielectric constant gate insulating film extends continuously from under the gate electrode to under the first insulating sidewall.
• The portion of the high dielectric constant gate insulating film under the first insulating sidewall is thinner than the portion under the gate electrode, for the reasons of managing capacitance and implantation difficulty.

Independent Method Claim 1 Overview:

This claim outlines a method for fabricating a semiconductor device, involving the steps of:
a) Forming a high dielectric constant gate insulating film on an active region of a substrate.
b) Forming a gate electrode on the high dielectric constant gate insulating film.
c) Etching, after step b), part of the high dielectric constant gate insulating film located in an external side to the gate electrode to reduce a thickness of the part.
d) Forming, after step c), an insulating sidewall on a side surface of the gate electrode.

Combination 3: Ken Watanabe (2005) + General semiconductor fabrication techniques

Prior Art Teaching:

• Ken Watanabe (2005): This reference, as described in US8587076, details the basic structure of a MISFET, including the formation of a high dielectric constant gate insulating film, a gate electrode on it, and insulating sidewalls on the sides of the gate electrode. These are fundamental steps in MISFET fabrication.

Motivation to Combine/Modify:
A POSITA would be aware that forming a high dielectric constant gate insulating film, a gate electrode, and sidewalls are standard steps in MISFET fabrication. The challenge articulated in US8587076 is how to keep the high-k film continuous under the sidewalls and reduce its thickness in that region to overcome issues like increased capacitance and difficult implantation.

The method claim introduces a specific sequence:

1. Forming the high-k gate insulating film. (Standard)
2. Forming the gate electrode. (Standard)
3. Etching the external part of the high-k film to reduce thickness after gate electrode formation.
4. Forming the insulating sidewall. (Standard)

The critical step here is (c) – selectively etching the high-k film after the gate electrode is formed and before the main sidewall is formed. A POSITA would be motivated to perform this etching step to address the problems outlined in the patent:

• Facilitate implantation: The patent explicitly states that reducing the thickness of the high dielectric constant gate insulating film in the external side to the gate electrode suppresses the increase in acceleration energy required for ion implantation (for extension or LDD regions), thereby enabling the formation of a shallow junction. This directly motivates the etching step (c).
• Reduce parasitic capacitance: Reducing the thickness of the high-k film under where the sidewall will be formed would also be understood to reduce parasitic capacitance between the gate and source/drain regions.

Given that etching is a very common semiconductor manufacturing technique, and selective etching processes (e.g., wet etching using hydrofluoric acid or selective dry etching, as mentioned in the patent) are well-known to a POSITA, modifying the thickness of a film at a specific location by etching would be a routine and predictable process. Performing this etching after the gate electrode acts as a self-aligned mask for the central gate region, ensuring the thickness under the gate remains higher. Performing it before the main sidewall allows for the desired thinning under the eventual sidewall.

Conclusion for Method Claim 1:
A POSITA, starting from the conventional MISFET fabrication process (as generally understood and exemplified by Watanabe's structures) and motivated to overcome the known technical problems of high gate-to-drain capacitance and deep junctions when using thick high-k gate dielectrics under sidewalls, would find it obvious to introduce a selective etching step (c) after gate electrode formation and before sidewall formation. This step directly addresses the identified problems by reducing the high-k film's thickness in the extension regions, leading to predictable improvements in device characteristics (shallower junctions) and circuit speed (reduced capacitance).