Derivative works — US Patent 8587076

Defensive Disclosure Document for US Patent 8587076

Current Date: April 26, 2026

This document outlines derivative variations of the core claims of US Patent 8587076, intended as defensive disclosures to establish prior art for future incremental improvements by competitors, rendering such improvements obvious or non-novel. The analysis is based on the independent device claim 1 and independent method claim 1 as inferred from the patent summary.

Derivatives of Independent Device Claim 1 Overview: Semiconductor Device Structure

(Core Idea: High dielectric constant gate insulating film continuously extending from under the gate electrode to under the insulating sidewall, with the portion under the sidewall having a smaller thickness than the portion under the gate electrode.)

1. Material & Component Substitution: Graphene/hBN High-k Stack with Metal Gate on SiC Substrate

Enabling Description: A semiconductor device comprising a wide-bandgap silicon carbide (SiC) substrate configured with an active region for high-power, high-frequency applications. A novel gate insulating stack is formed directly on a passivating, few-layer graphene buffer atop the SiC active region. This stack utilizes hexagonal boron nitride (hBN) as the high dielectric constant material, leveraging its atomically thin, high-k properties. The hBN film is continuously formed, extending from under a titanium nitride (TiN) metal gate electrode to under a silicon nitride (SiN) insulating sidewall. Crucially, the hBN film under the SiN sidewall is precisely controlled to a thickness of 1-2 atomic layers (approximately 0.3-0.6 nm), while the portion under the TiN gate electrode is 5-7 atomic layers thick (approximately 1.5-2.1 nm). This extreme thickness differential facilitates quantum tunneling for enhanced gate control in the extension region, while minimizing gate-to-source/drain capacitance. The TiN metal gate replaces traditional polysilicon, offering improved work function tunability and eliminating gate depletion effects.

Mermaid Diagram:

classDiagram
    Substrate "SiC" <|-- ActiveRegion
    ActiveRegion "with Graphene Buffer" *-- hBN_HighK_Film
    hBN_HighK_Film "Continuous" -- TiN_Gate_Electrode
    hBN_HighK_Film "Continuous" -- SiN_Sidewall
    TiN_Gate_Electrode -- hBN_HighK_Film : 5-7 AL Thick
    SiN_Sidewall -- hBN_HighK_Film : 1-2 AL Thick
    hBN_HighK_Film <|-- ExtensionRegion
    hBN_HighK_Film <|-- SourceDrainRegions
    class hBN_HighK_Film {
        +thicknessUnderGate
        +thicknessUnderSidewall
        +continuity
    }
    class TiN_Gate_Electrode {
        +metalGate
        +workFunctionTuning
    }
    class SiC_Substrate {
        +wideBandgap
        +highFrequency
    }

2. Operational Parameter Expansion: Cryogenic THz Transistor for Quantum Computing Interfaces

Enabling Description: A MISFET device specifically engineered for operation within a dilution refrigerator environment, targeting cryogenic temperatures (e.g., 4 Kelvin down to millikelvin range) and terahertz (THz) frequencies, making it suitable for quantum computing control and readout interfaces. The active region is established in an ultra-pure silicon-28 substrate to minimize nuclear spin decoherence. The high dielectric constant gate insulating film, composed of epitaxially grown Hafnium Dioxide (HfO2), is precisely sculpted with a thickness gradient: approximately 10 nm under the gate electrode (composed of superconducting Niobium Nitride, NbN) and gradually tapering to 2 nm under amorphous silicon (a-Si) insulating sidewalls. This meticulous thickness control is paramount for achieving ultra-low leakage currents at cryogenic temperatures, preventing thermal noise. Simultaneously, the pronounced tapering facilitates strong capacitive coupling to the extension region for ultra-fast switching characteristics required for THz operations, essential for rapidly manipulating and reading out superconducting qubits while minimizing cross-talk and decoherence.

Mermaid Diagram:

stateDiagram
    direction LR
    Off --> On : Gate Signal @ THz
    On --> Off : Gate Signal @ THz
    Off --> Standby : Low Power Mode
    Standby --> Off : Timeout
    Standby --> On : Wakeup Signal
    state DeviceOperating {
        state CryogenicEnvironment {
            state TemperatureRange {
                T_4K : 4 Kelvin
                T_mK : MilliKelvin
            }
            state FreqRange {
                THz_Ops : Terahertz Frequencies
            }
        }
        state HfO2GateDielectric {
            ThickUnderGate : 10nm (Under NbN Gate)
            ThinUnderSidewall : 2nm (Under a-Si Sidewall)
        }
    }
    ThickUnderGate --> ThinUnderSidewall : Tapering Gradient

3. Cross-Domain Application: Radiation-Hardened Power MISFET for Space Applications

Enabling Description: A large-area, high-power MISFET designed for robust operation in severe radiation environments characteristic of deep-space missions and satellite electronics. The device is fabricated on a Silicon-On-Insulator (SOI) substrate, providing intrinsic radiation hardness against latch-up and single-event upsets. The high dielectric constant gate insulating film, a Hafnium Silicate (HfSiO) with carefully integrated cerium oxide (CeO2) dopants for enhanced radiation tolerance, is continuously formed. This film exhibits a graded thickness, transitioning from a robust 20 nm under a Tungsten (W) metal gate electrode to a thinner 8 nm under thick, multi-layered insulating sidewalls composed of stacked alumina (Al2O3) and silicon oxynitride (SiON). This design concurrently optimizes gate coupling efficiency crucial for high-current power switching, while providing maximum resilience against total ionizing dose (TID) degradation and single-event effects (SEE). The thinner high-k region under the sidewall contributes to minimizing parasitic gate-drain capacitance, enabling higher switching frequencies in compact, radiation-hardened power conversion units.

Mermaid Diagram:

flowchart TD
    A[SOI Substrate] --> B(Active Region)
    B --> C{HfSiO:CeO2 High-K Film}
    C -- Thicker (20nm) --> D[W Metal Gate]
    C -- Thinner (8nm) --> E[Al2O3/SiON Sidewall]
    D -- Controls --> F(Power Switching Transistor)
    E -- Defines --> G(Extension Region)
    H[Radiation Environment] -- Impacts --> F
    I[High Power Load] -- Drives --> F
    F -- Resilient against --> H
    F -- Efficient for --> I
    subgraph Power MISFET Structure
        D
        E
        G
    end

4. Integration with Emerging Tech: AI-Optimized Self-Correcting MISFET with Integrated IoT Monitoring

Enabling Description: A semiconductor device featuring a MISFET fabricated with an active region on a conventional silicon substrate. The high dielectric constant gate insulating film, composed of HfZrOx (Hafnium Zirconium Oxide), is formed and then selectively etched to achieve a precise convex profile: 3 nm thickness under the polysilicon gate electrode and a tapered 1.5 nm thickness under the silicon oxide (SiO2) insulating sidewall. Critically, this etching process is entirely controlled by an on-chip AI agent, leveraging real-time, in-situ metrology data (e.g., broadband spectroscopic ellipsometry, optical critical dimension sensors). The AI dynamically adjusts etch parameters (plasma power, gas flow, etch time) to compensate for process variations and achieve optimal thickness uniformity and gradient across the wafer. The MISFET itself incorporates integrated IoT micro-sensors (e.g., embedded temperature, voltage, and current leakage monitors) that provide continuous, real-time feedback on device performance, threshold voltage stability, and hot carrier injection. This sensor data is fed back to the AI system for adaptive power management, predictive failure analysis, and autonomous self-calibration, maximizing device lifespan and ensuring sustained performance under varying operational loads.

Mermaid Diagram:

sequenceDiagram
    participant AI_Agent as AI Optimization Agent
    participant Metrology as In-situ Metrology System
    participant Etcher as Plasma Etch Tool
    participant MISFET as Fabricated MISFET Device
    participant IoT_Sensors as Integrated IoT Sensors

    AI_Agent->Etcher: Set Initial Etch Parameters
    loop Real-time Optimization
        Metrology->Etcher: Capture Pre-Etch Data
        Etcher->Metrology: Perform Etch Step
        Metrology->AI_Agent: Send Post-Etch Thickness Data
        AI_Agent->Etrology: Compare to Target Profile
        AI_Agent->Etcher: Adjust Etch Parameters (Feedback Loop)
    end
    Etcher->MISFET: Complete MISFET Fabrication (Tapered High-K)
    loop Continuous Monitoring
        IoT_Sensors->MISFET: Monitor Vth, Leakage, Temp
        IoT_Sensors->AI_Agent: Transmit Performance Data
        AI_Agent->MISFET: Recommend Adaptive Power Mgmt
    end

5. The "Inverse" or Failure Mode: Adaptive Low-Power Mode MISFET with Gate-Edge Sacrificial Dielectric

Enabling Description: A semiconductor device incorporating a MISFET engineered for graceful degradation and an adaptive low-power operational mode upon detecting impending failure. The active region is formed in a standard silicon well. The gate insulating film is a composite stack, featuring a primary high-k material (e.g., HfO2) and an ultra-thin, highly resistive sacrificial layer (e.g., amorphous carbon or a doped silicon oxide) strategically placed at the gate-edge. The HfO2 film is 4 nm thick under the polysilicon gate electrode, and tapers to 2 nm under the silicon nitride (SiN) insulating sidewall. The sacrificial layer is deposited directly on top of this thinner HfO2 region, extending laterally beyond the gate-edge. In normal operation, the sacrificial layer maintains full insulation. However, upon detection of an over-voltage event, excessive temperature, or abnormal leakage, the sacrificial layer is designed to locally increase its resistance or undergo a controlled, non-catastrophic breakdown in a predictable manner. This localized degradation prevents irreversible damage to the primary HfO2 film, allowing the device to transition into a safe, reduced-performance, low-power mode (e.g., increased gate leakage but still retaining basic switching functionality, or complete disablement of that specific transistor block) rather than experiencing a hard, catastrophic failure. This "graceful degradation" capability enhances system reliability and fault tolerance.

Mermaid Diagram:

stateDiagram
    Device_Normal --> Device_Degraded : Over-Voltage/Temp/Leakage Detected
    Device_Degraded --> Device_Low_Power : Sacrificial Dielectric Breakdown
    Device_Normal --> Device_Fail_Catastrophic : Uncontrolled Failure (Prevented)
    Device_Low_Power --> Device_Off : System Shutdown
    Device_Degraded --> Device_Degraded : Continue Limited Functionality

    state Device_Normal {
        Gate_Control : Optimal
        Leakage : Low
        Performance : Full
    }

    state Device_Degraded {
        Sacrificial_Dielectric : Broken down/High R
        Primary_Dielectric : Intact
        Leakage : Increased
        Performance : Reduced
    }

    state Device_Low_Power {
        Power_Consumption : Minimized
        Functionality : Limited
        Gate_Control : Basic
    }

Derivatives of Independent Method Claim 1 Overview: Semiconductor Device Fabrication Method

(Core Idea: Forming high-k film, forming gate electrode, etching part of high-k film external to gate electrode to reduce thickness, forming insulating sidewall.)

1. Material & Component Substitution: Atomic Layer Etching (ALE) for High-k Tapering

Enabling Description: A method for fabricating a semiconductor device, comprising the steps of: a) forming a high dielectric constant gate insulating film, specifically aluminum oxide (Al2O3), on an active region of a silicon-germanium (SiGe) substrate, optimized for strained-channel transistors. b) Forming a metal gate electrode, such as titanium aluminum (TiAl), on the Al2O3 high-k film. c) Performing atomic layer etching (ALE), after step b), to selectively reduce the thickness of the Al2O3 high-k film located external to the TiAl metal gate electrode. This ALE process utilizes precise, sequential, self-limiting gas-phase reactions (e.g., alternating cycles of chlorine (Cl2) plasma exposure for surface modification followed by argon (Ar) purging and ion bombardment for material removal). This enables sub-nanometer etching control to achieve a thickness reduction from an initial 5 nm to 2 nm in the external regions, with minimal damage to the remaining film and a highly controlled, near-atomic-scale taper angle at the gate edge. This technique offers superior control compared to conventional wet or dry etching methods for advanced nodes. d) Subsequently forming an insulating sidewall, composed of a low-k dielectric material such as SiCOH (silicon oxycarbide), on a side surface of the TiAl gate electrode.

Mermaid Diagram:

flowchart TD
    A[Form Al2O3 High-K on SiGe Substrate] --> B[Form TiAl Gate Electrode]
    B --> C{ALE Process - Selective Etching}
    C -- Step 1: Surface Adsorption --> C1[Cl2 Plasma Exposure]
    C1 -- Step 2: Desorption/Removal --> C2[Ar Purge & Ion Bombardment]
    C2 -- Repeat Cycles --> C3[Achieve 5nm to 2nm Thickness Reduction]
    C3 --> D[Form SiCOH Insulating Sidewall]
    D --> E[Completed Device Structure]

2. Operational Parameter Expansion: High-Throughput Cryo-Etching of High-k for 3D-Stacked Devices

Enabling Description: A method for high-volume fabrication of advanced 3D-stacked integrated circuits, involving: a) forming a high dielectric constant gate insulating film, specifically HfSiON, on an active region of a large-diameter (e.g., 450mm) silicon wafer, which may already incorporate through-silicon vias (TSVs). b) Forming a gate electrode, either polysilicon or tungsten (W), on the HfSiON film. c) Employing cryogenic dry etching (e.g., utilizing a sulfur hexafluoride (SF6) and oxygen (O2) plasma at a substrate temperature of -100°C to -150°C) after step b). This method selectively reduces the thickness of the HfSiON film located external to the gate electrode, achieving a precise reduction from an initial 4 nm to 1.5 nm. Cryogenic etching provides enhanced selectivity to the underlying substrate and minimizes plasma-induced damage to the gate sidewalls, crucial for maintaining device integrity in multi-layer 3D stacks. The process is optimized for high throughput and maintains critical dimension uniformity across the entire large-diameter wafer, enabling efficient manufacturing of complex 3D architectures. d) Finally, forming an insulating sidewall, such as a bilayer of SiO2/SiN, on a side surface of the gate electrode.

Mermaid Diagram:

flowchart TD
    A[Prepare 450mm Wafer with TSVs] --> B[Form HfSiON High-K Film]
    B --> C[Form Poly-Si/W Gate Electrode]
    C --> D{Cryogenic Dry Etching}
    D -- Plasma Chemistry --> D1[SF6/O2 Plasma]
    D -- Temperature --> D2[Substrate @ -100C to -150C]
    D -- Etch Parameters --> D3[Optimize Selectivity & Anisotropy]
    D3 --> E[Reduce High-K Thickness (4nm to 1.5nm)]
    E --> F[Form SiO2/SiN Bilayer Sidewall]
    F --> G[Completed 3D-Stacked MISFET Layer]

3. Cross-Domain Application: Microfluidic-Assisted Chemical Mechanical Polishing (CMP) for Biosensor FETs

Enabling Description: A novel method for fabricating a Bio-FET (Field-Effect Transistor) sensor with enhanced sensitivity and reduced parasitic capacitance. This method involves: a) forming a high dielectric constant gate insulating film, specifically Tantalum Pentoxide (Ta2O5) due to its excellent biocompatibility and high dielectric constant, on an active sensing region of a silicon substrate. b) Forming a gate electrode, composed of biocompatible Platinum (Pt), on the Ta2O5 film. c) Performing a localized, microfluidic-assisted chemical mechanical polishing (CMP), after step b), to selectively reduce the thickness of the Ta2O5 film external to the Pt gate electrode. A precisely formulated, low-abrasion, biocompatible chemical slurry is delivered and recirculated through microfluidic channels precisely patterned onto a temporary polymer mask over the wafer. This microfluidic delivery system allows for highly localized and gentle thinning of the Ta2O5 dielectric in the specific biosensing region (e.g., from 6 nm to 3 nm), enabling fine control over the gate-sensing interface properties while minimizing mechanical stress. d) Forming a protective, biocompatible insulating sidewall, such as parylene-C, on a side surface of the Pt gate electrode, encapsulating the thinned Ta2O5 region and defining the active sensing window.

Mermaid Diagram:

flowchart TD
    A[Prepare Si Substrate with Active Sensing Region] --> B[Form Ta2O5 High-K Film]
    B --> C[Form Pt Gate Electrode]
    C --> D{Microfluidic-Assisted CMP}
    D -- Slurry Delivery --> D1[Microfluidic Channels]
    D -- Chemical Action --> D2[Low-Abrasion Slurry]
    D -- Mechanical Action --> D3[Localized Polishing]
    D3 --> E[Reduce Ta2O5 Thickness (6nm to 3nm)]
    E --> F[Form Parylene-C Sidewall (Biocompatible)]
    F --> G[Completed Bio-FET Sensor]

4. Integration with Emerging Tech: Reinforcement Learning (RL) Controlled Plasma Etching for Adaptive Device Design

Enabling Description: A fabrication method for semiconductor devices utilizing an active region on a standard silicon substrate. This method includes: a) forming a high dielectric constant gate insulating film, such as HfO2, with an initial uniform thickness. b) Forming a gate electrode, composed of polysilicon, on the HfO2 film. c) Executing a plasma etching step controlled by a reinforcement learning (RL) agent, after step b). The RL agent, operating within a digital twin simulation environment and continuously validated with in-situ metrology data, dynamically adjusts plasma parameters (e.g., radio-frequency power, gas flow ratios, chamber pressure, bias voltage) in real-time. This adaptive control allows for the creation of complex, non-uniform thickness profiles for the HfO2 film external to the gate electrode, transcending fixed-recipe limitations. The RL agent optimizes for specific device performance targets, such as a precise threshold voltage (Vt) gradient or optimized leakage current profile across different functional blocks of the integrated circuit, by tailoring the HfO2 thickness reduction (e.g., varying from 4 nm down to 1 nm with specific, spatially-dependent taper angles). d) Subsequently forming an insulating sidewall, typically silicon nitride (SiN), on a side surface of the gate electrode.

Mermaid Diagram:

sequenceDiagram
    participant RL_Agent as Reinforcement Learning Agent
    participant Sim_Env as Digital Twin Simulation
    participant Metrology as In-situ Metrology
    participant Plasma_Etcher as Plasma Etch Tool
    participant HfO2_Film as HfO2 High-K Film

    RL_Agent->Sim_Env: Explore Etch Parameter Space
    Sim_Env->RL_Agent: Provide Performance Feedback (Reward)
    loop Continuous Learning
        RL_Agent->Plasma_Etcher: Propose Etch Parameters
        Plasma_Etcher->HfO2_Film: Execute Etch Step
        HfO2_Film->Metrology: Acquire Real-time Thickness Data
        Metrology->RL_Agent: Update Observation (State)
        RL_Agent->Plasma_Etcher: Adjust Parameters (Policy Update)
    end
    Plasma_Etcher->HfO2_Film: Achieve Adaptive Thickness Profile

5. The "Inverse" or Failure Mode: "Fuse-Enabled" High-k Thickness Reduction with Intentional Breakdown Points

Enabling Description: A method for fabricating a semiconductor device featuring integrated stress-relief and over-current protection mechanisms directly within the gate dielectric structure. The method comprises: a) forming a high dielectric constant gate insulating film, specifically Zirconium Dioxide (ZrO2), on an active region of a substrate. b) Forming a gate electrode, typically polysilicon, on the ZrO2 film. c) Implementing a two-stage etching process after step b): first, a blanket, uniform thickness reduction etch across the entire external ZrO2 film (e.g., from 4 nm to 2 nm); followed by a highly localized, precise over-etch of specific, pre-defined points or lines within the ZrO2 film external to the gate electrode. This targeted over-etch creates regions of extremely thin ZrO2 (e.g., less than 1 nm, or even partially removed down to the substrate interface) at strategic locations. These ultra-thin regions are designed to act as "fuse-points" or controlled dielectric breakdown zones, engineered to intentionally degrade or electrically short under excessive electrical or thermal stress (e.g., over-voltage, over-current events). This controlled failure prevents catastrophic damage to the main device and allows for system-level protection, diverting current paths, or isolating a failed transistor block, enabling the device to enter a safe, non-operational, or isolated state. d) Subsequently, forming an insulating sidewall, such as silicon oxide (SiO2), on a side surface of the gate electrode, encapsulating and protecting these strategically weakened ZrO2 fuse-points.

Mermaid Diagram:

flowchart TD
    A[Form ZrO2 High-K on Substrate] --> B[Form Poly-Si Gate Electrode]
    B --> C{Two-Stage Etching Process}
    C -- Stage 1: Uniform Reduction --> C1[Reduce ZrO2 (4nm to 2nm) External to Gate]
    C1 -- Stage 2: Localized Over-Etch --> C2[Create Ultra-Thin ZrO2 Regions (Fuse-Points)]
    C2 --> D[Form SiO2 Insulating Sidewall]
    D --> E[Completed Device with Fuse-Enabled High-K]
    subgraph Failure Mode Response
        E -- Over-Stress --> F(Fuse-Points Degrade/Short)
        F --> G(Prevent Catastrophic Device Failure)
        G --> H(System Enters Safe/Isolated State)
    end

Combination Prior Art Scenarios

SEMI E10-1209 - Specification for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM) and Utilization:
- Scenario: A semiconductor fabrication facility employs a manufacturing execution system (MES) and process control system (PCS) that are fully compliant with SEMI E10-1209. The method for fabricating semiconductor devices, as detailed in Independent Method Claim 1 and its derivatives (e.g., "Reinforcement Learning (RL) Controlled Plasma Etching for Adaptive Device Design"), is integrated into this compliant framework. The RL agent's dynamic adjustments to plasma parameters are not only optimized for high-k thickness profiles but also directly feed into the E10 RAM metrics. Real-time sensor data from the in-situ metrology (e.g., ellipsometry, OCD) and device performance monitors (e.g., IoT sensors within "AI-Optimized Self-Correcting MISFET") are captured, standardized, and reported according to SEMI E10, enabling precise calculation of equipment uptime, mean time between failures (MTBF), and overall equipment effectiveness (OEE) for each etch tool and process step. This ensures that the advanced high-k gate stack fabrication contributes directly to the overall operational efficiency and reliability targets of the fab, providing a closed-loop system for continuous improvement aligned with industry standards for equipment performance.
RISC-V ISA (Instruction Set Architecture) Standard (e.g., RV64GC):
- Scenario: A high-performance, low-power 64-bit RISC-V processor core, designed in accordance with the RV64GC (general-purpose 64-bit with atomic, compressed, and floating-point extensions) instruction set architecture, is implemented using MISFETs fabricated with the specific high dielectric constant gate insulating film structure of US8587076 (Independent Device Claim 1 and its derivatives, particularly "Graphene/hBN High-k Stack with Metal Gate on SiC Substrate"). The unique tapered high-k dielectric, with its thinner portion under the sidewall, is critical for achieving the stringent power and performance targets for next-generation RISC-V designs. This structure inherently reduces parasitic gate-drain/source capacitance and enhances gate control at scaled dimensions, directly improving the switching speed and reducing static and dynamic power consumption of the individual transistors within the RISC-V execution units, register files, and cache memory. The open-source nature of RISC-V means that the benefits of this advanced transistor architecture can be rapidly disseminated and adopted by a broad community of hardware developers.
Open-Source Process Design Kit (PDK) based on SkyWater SKY130 technology:
- Scenario: The innovative high dielectric constant gate insulating film structure and its associated fabrication method described in US8587076 (Independent Device Claim 1 and Independent Method Claim 1) are incorporated as a foundational component within an open-source Process Design Kit (PDK), specifically building upon the widely utilized SkyWater SKY130 technology. This integration would involve developing new device models (e.g., SPICE models), layout rules, and process specifications within the PDK to accurately represent the tapered high-k gate dielectric. Foundry users and open-source chip designers would then be able to leverage this advanced transistor architecture to design custom integrated circuits. For example, the "Adaptive Low-Power Mode MISFET" derivative could be offered as a specific device option, allowing designers to specify transistors with built-in graceful degradation for critical low-power or safety-critical functions within their SkyWater SKY130-based designs, extending the capabilities and design flexibility of the open-source PDK ecosystem.