US 8234483

Here's a concise summary of US Patent 8234483:

Title: Memory units with packet processor for decapsulating read write access from and encapsulating response to external devices via serial packet switched protocol interface

Assignee: Edgecomm LLC (Current Assignee as of 2025-10-10) (Original Assignee: Psimast Inc)

Inventor: Viswa Nath Sharma

Filing Date: 2010-10-25

Issue Date: 2012-07-31

Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

---

Plain-Language Overview of Independent Claims:

• Claim 1 (Apparatus): This claim describes a chip architecture for integrated circuitry. It includes at least one memory device and a unique packet processor associated with each memory device, both co-located on a semiconductor die package. The packet processor provides read and write access to the memory device for an external device. It does this by taking incoming packets (from the external device) that conform to a serial protocol, decapsulating the address, data, and control information, and then encapsulating data (including the decapsulated address and control information) into a new packet conforming to the same serial protocol to send back to the external device in response. This communication occurs over at least one high-speed packet switched serial interface, which is accessible via an external port on the semiconductor die package.

• Claim 6 (Method): This claim outlines a method for implementing the chip architecture described in Claim 1. It involves providing a semiconductor die package with co-located memory devices and associated packet processors. The method includes the steps performed by the packet processor as described in Claim 1: decapsulating information from received serial packets for memory access and encapsulating response data into serial packets for transmission back to the external device, all via a high-speed packet switched serial interface.

• Claim 11 (Computer Readable Media): This claim covers computer-readable media containing instructions for implementing the chip architecture. These instructions define the co-located memory device(s) and associated packet processor(s) on a semiconductor die package, where the packet processor functions to decapsulate and encapsulate information for external device memory access via a high-speed packet switched serial interface, as detailed in Claim 1. The instructions also define at least one external port for accessing this interface.

---

CAFC 2026 Dockets:
As of April 26, 2026, a search of the CAFC 2026 dockets did not return any specific litigation mentioning US patent 8234483. The search results provided information on other patent cases (e.g., US Patent No. 8,458,689) and general CAFC activity, but not for 8234483.