Invalidity dossier
US 8193878
Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance
Current assignee: GlobalFoundries US Inc
Added 9/23/2026, 12:12:04 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview: US 8,193,878 B2
Title: Structure, structure and method for providing an on-chip variable delay transmission line with fixed characteristic impedance
Patent Number: US 8,193,878 B2 (Application No. US 12/144,684)
Inventors: Hanyi Ding; Wayne H. Woods, Jr.
Original Assignee: International Business Machines Corp. (Current assignee listed as GlobalFoundries US Inc.)
Key Dates: Priority/filing date: 2008-06-24; Publication date: 2012-06-05; Adjusted expiration listed as 2030-09-06; legal status listed as Active.
Purpose: The patent addresses delay lines used to adjust signal timing and impart phase shifts, including in phased arrays for applications such as RADAR and data communications. Conventional approaches that provide each antenna element with multiple transmission lines selected by a switch are described as costly in footprint and manufacturing, and as causing signal attenuation. The invention aims to provide a single on-chip structure whose delay can be varied while characteristic impedance remains relatively constant.
Plain-Language Scope: According to the supplied text, the disclosure covers a transmission line structure with a signal line and plural selectable ground return structures. A first ground return structure causes a first delay and first characteristic impedance; a second ground return structure causes a second, different delay but substantially the same characteristic impedance. A switch grounds one ground return structure while floating the other. The structures may be formed across different wiring levels of a semiconductor structure. Ground return structures may include a ground return rail and a capacitance structure, with the first rail positioned further from the signal line than the second rail, and the first capacitance structure closer to the signal line than the second. The disclosure also covers a semiconductor structure, a design structure embodied in a machine-readable medium, and an HDL design structure.
Source: https://patents.google.com/patent/US8193878/en
What the excerpt does not establish: It provides only partial description text and figure listings (FIGS. 1–17), without full claims, detailed embodiments, or the complete specification. It therefore does not establish the precise claim scope, dimensions, materials, fabrication details, or the full nature of the described process and design-flow steps.
Generated 10/1/2026, 9:53:47 PM
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Litigation summary
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PTAB challenges
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Assignment history
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Prior art
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Obviousness
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Extensions
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Derivative works
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