Prior art

To find the most relevant prior art for US patent 8,076,735, I will examine the patent citations listed within the patent itself. The USPTO provides resources for searching patent databases and prior art. Prior art includes publicly known information before the effective filing date of a patent application, such as U.S. patents, foreign patents, and published applications.

Here's an analysis of the patent citations for US8076735, focusing on their potential anticipation under 35 U.S.C. § 102.

Cited Patents (Examiner Cited, unless otherwise noted):

• US5834816A (Goldstar Electron Co., Ltd.)

  • Publication Date: November 10, 1998
  • Description: This patent describes a MOSFET having a tapered gate electrode. The tapering is generally aimed at reducing short channel effects and improving device performance.
  • Potential Anticipation (35 U.S.C. § 102): May anticipate elements of Claim 1, particularly regarding the concept of a non-uniform (tapered) gate electrode or trench shape, if the specific "neck narrower than top" and "neck narrower than or equal to bottom" features of the trench in US8076735 are considered to be an ordinary tapering. However, US8076735 specifies a unique funnel-like or wide-top/narrow-bottom trench profile created by differential etching rates based on dopant concentration, which might differentiate it from a general tapered gate.

• US5840611A (Goldstar Electron Company, Ltd.)

  • Publication Date: November 24, 1998
  • Description: This patent describes a process for making a semiconductor MOS transistor. Similar to US5834816A, it likely deals with aspects of gate electrode formation and device structure.
  • Potential Anticipation (35 U.S.C. § 102): Similar to US5834816A, it could potentially anticipate the broad concept of forming MOS transistors with shaped gate electrodes. The specific method of doping a polysilicon layer to control etching rates and create a unique trench profile, as detailed in US8076735, would be a key differentiator.

• US5685950A (Sony Corporation)

  • Publication Date: November 11, 1997
  • Description: This patent describes a dry etching method. Etching processes are crucial in semiconductor fabrication for creating desired patterns and shapes.
  • Potential Anticipation (35 U.S.C. § 102): Could potentially anticipate the general use of dry etching in semiconductor fabrication (as mentioned in the detailed description of US8076735 for forming dummy patterns using a halogen-containing reactant). However, it is unlikely to anticipate the specific method of controlling the etching rate via N-type dopant concentration in a polysilicon layer to achieve the specific dummy pattern/trench shape of US8076735.

• JPH0855863A (Nec Corp)

  • Publication Date: February 27, 1996
  • Description: This Japanese patent application describes the manufacture of a field-effect semiconductor device. Without a full English translation, specific details are hard to ascertain, but it likely covers aspects of FET fabrication.
  • Potential Anticipation (35 U.S.C. § 102): General claims about FET manufacturing might be broad enough to encompass some aspects, but the specific trench geometry and formation method of US8076735 would likely provide novelty.

• US6060375A (Lsi Logic Corporation)

  • Publication Date: May 9, 2000
  • Description: This patent describes a process for forming a re-entrant geometry for a gate electrode of an integrated circuit structure. A re-entrant geometry often implies an undercut or wider opening at the top, which is relevant to US8076735's "wide opening in the top" feature.
  • Potential Anticipation (35 U.S.C. § 102): This patent appears highly relevant to Claim 1 of US8076735, particularly the "width of the neck is narrower than a width of the top" aspect of the trench. The method of forming this re-entrant geometry would need to be compared to the N-type dopant-controlled etching of US8076735 to determine if the specific method of achieving the re-entrant shape is anticipated, or just the resulting shape itself. If the re-entrant shape is inherently similar and achieved by a known method, it could anticipate this aspect of the claim.

• US5879975A (Advanced Micro Devices, Inc.)

  • Publication Date: March 9, 1999
  • Description: This patent describes heat treating a nitrogen implanted gate electrode layer for improved gate electrode etch profile. This indicates an awareness of using implantation and heat treatment to influence etch profiles.
  • Potential Anticipation (35 U.S.C. § 102): This could potentially anticipate the general idea of using implantation to modify etching characteristics of a gate electrode layer, which is a core part of the method in US8076735. However, the specific N-type dopants (P, Sb, As) in polysilicon and their effect on etching rates to create the precise "neck narrower than top" and "neck narrower than or equal to bottom" profile would need detailed comparison.

• US6661066B2 (Mitsubishi Denki Kabushiki Kaisha)

  • Publication Date: December 9, 2003
  • Description: This patent describes a semiconductor device including an inversely tapered gate electrode and a manufacturing method thereof. An inversely tapered gate could potentially refer to a structure where the top is wider than a lower portion, aligning with the concept of a "neck narrower than top" in US8076735.
  • Potential Anticipation (35 U.S.C. § 102): Similar to US6060375A, this patent is highly relevant to Claim 1's trench shape. The key would be whether the "inversely tapered" definition specifically matches the "neck narrower than top, and narrower than or equal to bottom" of US8076735, and if the method of fabrication is similar enough to render the specific doping and etching of US8076735 obvious or anticipated.

• US6674137B2 (Nec Corporation)

  • Publication Date: January 6, 2004
  • Description: This patent describes a semiconductor device and its manufacturing method. Without further details on the specific device or method, its relevance is broad.
  • Potential Anticipation (35 U.S.C. § 102): Generic claims for semiconductor devices and manufacturing methods are unlikely to anticipate the specific trench geometry and fabrication method of US8076735 without more detailed correspondence.

• US7208361B2 (Intel Corporation)

  • Publication Date: April 24, 2007
  • Description: This patent describes a replacement gate process for making a semiconductor device that includes a metal gate electrode. US8076735 explicitly states it uses a "gate last process to form a complementary metal oxide semiconductor (CMOS) device," which is a type of replacement gate process.
  • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant to the overall gate last (or replacement gate) process described in US8076735. While it might not anticipate the specific trench shape, it could anticipate the broader method steps related to forming dummy patterns and then replacing them with metal gates. This might impact the novelty of method claims in a broader sense, but not necessarily the specific structural claims related to the trench shape.

• US20070126067A1 (Intel Corporation)

  • Publication Date: June 7, 2007
  • Description: This publication describes angled implantation for removal of thin film layers. Angled implantation can influence etch rates and profiles.
  • Potential Anticipation (35 U.S.C. § 102): This could potentially anticipate the concept of using ion implantation to affect the removal (etching) of layers. However, US8076735 focuses on vertical blanket doping to create a depth-dependent etch rate, resulting in a specific trench profile, which may be distinct from angled implantation for general thin film removal.

• US20090189219A1 (Shinbori Atsushi)

  • Publication Date: July 30, 2009
  • Description: This publication describes a semiconductor device and a manufacturing method of the same. The priority date of US8076735 is October 2, 2009, so this publication is prior art. Specific details would be needed to assess anticipation.
  • Potential Anticipation (35 U.S.C. § 102): Without specific details from the publication, it's difficult to assess. However, given its close publication date to the filing of US8076735, it could potentially contain similar advancements in semiconductor device fabrication or gate structures.

• US20090218603A1 (Brask Justin K)

  • Publication Date: September 3, 2009
  • Description: This publication describes semiconductor device structures and methods of forming semiconductor structures. Similar to US20090189219A1, this is also prior art due to its publication date before the filing of US8076735.
  • Potential Anticipation (35 U.S.C. § 102): Like the previous publication, a detailed comparison of its disclosed structures and methods to those claimed in US8076735 would be necessary.

• US7749911B2 (Taiwan Semiconductor Manufacturing Co., Ltd.)

  • Publication Date: July 6, 2010
  • Description: This patent describes a method for forming an improved T-shaped gate structure. A T-shaped gate typically has a wider top portion.
  • Potential Anticipation (35 U.S.C. § 102): This patent is particularly relevant to Claim 1 of US8076735 due to its focus on non-rectangular gate shapes with wider top portions. While the publication date is after the filing date of US8076735, its priority date would be critical in a 35 U.S.C. § 102 analysis. If its priority date predates US8076735, and its T-shaped gate structure with a wider top is sufficiently similar to the "neck narrower than top" feature, it could be highly anticipatory. The specific dimensions and the method of achieving the T-shape would need to be compared against the N-type dopant-controlled etching for the funnel-like or wide-top/narrow-bottom shape in US8076735.

• US20110070702A1 (United Microelectronics Corp.)

  • Publication Date: March 24, 2011
  • Description: This publication describes a method for fabricating a semiconductor device. This appears to be an application by the same original assignee as US8076735. While the publication date is after US8076735's filing, its priority date might be earlier, or it could be a related or divisional application.
  • Potential Anticipation (35 U.S.C. § 102): As an application from the same assignee, it's less likely to be used for anticipation under § 102 against its own family unless it has a significantly earlier priority date for similar subject matter and is not considered a parent or divisional application. It is more likely to be considered for obviousness under 35 U.S.C. § 103, or perhaps as a related application containing overlapping subject matter.

• US7939895B2 (Sony Corporation)

  • Publication Date: May 10, 2011
  • Description: This patent describes a semiconductor device with a forwardly tapered P-type FET gate electrode and a reversely tapered N-type FET gate electrode and a method of manufacturing the same. This patent also directly addresses tapered gate electrodes in different FET types.
  • Potential Anticipation (35 U.S.C. § 102): This patent is also highly relevant to Claim 1 of US8076735, specifically regarding tapered gate electrodes and varying profiles for different transistor types. Similar to US7749911B2 and US6661066B2, a detailed comparison of the specific tapering, especially the "neck narrower than top, and narrower than or equal to bottom" aspect of the trench in US8076735, against the disclosed tapered profiles in this Sony patent would be crucial. The manufacturing method, particularly the use of differential etching based on N-type dopant concentration in polysilicon, would be a key point of distinction.