Obviousness

For a patent to be deemed obvious under 35 U.S.C. § 103, the differences between the claimed invention and the prior art must be such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA) to which said subject matter pertains. This assessment considers whether there was a motivation in the prior art to combine existing elements to achieve the claimed invention, with a reasonable expectation of success.

The independent claim of US Patent 8076735, Claim 1, describes a semiconductor device with a trench having a specific profile: a neck narrower than the top, and narrower than or equal to the bottom. This unique trench shape is key to the invention's benefits, such as void-free metal fill and unaffected critical dimensions. The method of achieving this shape, as detailed in the patent, involves doping a polysilicon layer with an N-type dopant to create differential etching rates.

To establish obviousness, one would need to demonstrate that a PHOSITA, at the time of the invention (October 2, 2009), would have been motivated to combine prior art references to arrive at this specific trench structure and the resulting semiconductor device, with a reasonable expectation of success.

Let's examine the cited prior art and consider potential combinations:

Prior Art References and their relevant disclosures:

• US5834816A (Goldstar Electron Co., Ltd.): Discloses a MOSFET having a tapered gate electrode. This suggests knowledge of controlling gate electrode shapes.
• US5840611A (Goldstar Electron Company, Ltd.): Describes a process for making a semiconductor MOS transistor.
• US5685950A (Sony Corporation): Pertains to a dry etching method.
• JPH0855863A (Nec Corp): Discloses the manufacture of a field-effect semiconductor device.
• US6060375A (Lsi Logic Corporation): Describes a process for forming re-entrant geometry for a gate electrode of an integrated circuit structure. "Re-entrant geometry" suggests non-uniform widths along the trench sidewalls, which is relevant to the "neck" feature of the present invention.
• US5879975A (Advanced Micro Devices, Inc.): Focuses on heat treating a nitrogen implanted gate electrode layer for an improved gate electrode etch profile. This teaches the concept of modifying polysilicon properties (via doping/implantation) to influence etching.
• US6661066B2 (Mitsubishi Denki Kabushiki Kaisha): Discloses a semiconductor device including an inversely tapered gate electrode and a manufacturing method. "Inversely tapered" could imply a wider bottom than top, or a non-uniform profile.
• US6674137B2 (Nec Corporation): Covers a semiconductor device and its manufacturing method.
• US7208361B2 (Intel Corporation): Deals with a replacement gate process for making a semiconductor device that includes a metal gate electrode. This establishes the "gate last" process context, which is the framework for US8076735.
• US20070126067A1 (Intel Corporation): Relates to angled implantation for removal of thin film layers, which is a technique for modifying etching characteristics.
• US20090218603A1 (Brask Justin K): Discusses semiconductor device structures and methods of forming semiconductor structures.
• US7749911B2 (Taiwan Semiconductor Manufacturing Co., Ltd.): Describes a method for forming an improved T-shaped gate structure. A T-shaped gate structure inherently has different widths at different vertical positions, similar to the concept of a neck.
• US20090189219A1 (Shinbori Atsushi): Pertains to a semiconductor device and a manufacturing method.
• US20110070702A1 (United Microelectronics Corp.): Describes a method for fabricating a semiconductor device. This is a related patent from the original assignee.
• US7939895B2 (Sony Corporation): Discloses a semiconductor device with a forwardly tapered P-type FET gate electrode and a reversely tapered N-type FET gate electrode and a method of manufacturing the same. This explicitly teaches varying gate electrode profiles for different transistor types.

Motivation to combine:

The primary motivation for a PHOSITA to combine these references would be to overcome the known problems in conventional gate-last processes, specifically the poor metal gap fill and void formation in trenches that are narrower at the top. The background of US8076735 explicitly states these problems, noting that "the resultant dummy patterns are usually shaped into trapezoids having a narrow top and a wide bottom, so that an included angle between the top sidewall of each the dummy pattern and the surface of the interlayer dielectric layer is about 88°-89°." This leads to "an opening with a narrower top portion" after dummy pattern removal, resulting in "poor metal gap fill effect" and "formation of voids in the metal layer." The invention aims to solve this by creating a trench with a "wider opening in a top" (i.e., an included angle greater than 90°) and a neck that is narrower than the top.

A PHOSITA would be looking for methods to improve metal gate fill and device reliability in gate-last processes.

Possible Obviousness Combinations:

1. US7208361B2 (Intel) + US5879975A (Advanced Micro Devices, Inc.) + US6060375A (Lsi Logic Corporation) / US7749911B2 (TSMC) / US7939895B2 (Sony)

   • US7208361B2 (Intel) establishes the context of a replacement gate process (gate-last process) for metal gate electrodes. This is the fundamental process flow that US8076735 seeks to improve.
   • US5879975A (Advanced Micro Devices, Inc.) teaches the concept of modifying polysilicon layers through implantation (e.g., nitrogen implantation) to achieve an improved etch profile. This directly provides the technical means for selectively altering etch rates within a polysilicon dummy gate.
   • US6060375A (Lsi Logic Corporation) discloses forming "re-entrant geometry" for gate electrodes. While not explicitly defining a "neck narrower than the top," it indicates an awareness and desire to create non-uniform gate electrode shapes. Alternatively, US7749911B2 (TSMC) describes T-shaped gate structures, which also exhibit varying widths along the vertical dimension. US7939895B2 (Sony) explicitly discusses forwardly and reversely tapered gate electrodes, demonstrating an understanding of intentionally designing gate profiles with different widths.
   • Motivation and Expectation of Success: Given the known problem of poor metal gap fill in narrow-top trenches in gate-last processes (as articulated in the background of US8076735), a PHOSITA would be motivated to create a trench with a wider top opening. By combining the replacement gate process of Intel with the knowledge of etch rate modification through doping (Advanced Micro Devices) and the general concept of forming non-uniform or re-entrant/tapered gate/trench geometries (Lsi Logic, TSMC, or Sony), a PHOSITA would have a strong motivation to use differential doping to create a dummy gate that results in a trench with a wider top and a narrower neck. The expectation of success would be reasonable because the principle of dopant-dependent etching of polysilicon was known, and the desired outcome (improved fill) directly addresses a recognized problem. The specific "funnel-like" or "wide top and narrow bottom" shapes described in US8076735 for the dummy patterns (and thus the inverse for the trenches) are a predictable result of applying a dopant with varying concentration, combined with an etching process sensitive to that dopant, as taught by Advanced Micro Devices.

2. US20070126067A1 (Intel) + H. Seidel et al., "Anisotropic Etching of Crystalline Silicon in Alkaline Solutions: II. Influence of Dopants"

   • US20070126067A1 (Intel) introduces the concept of angled implantation for removal of thin film layers, which implies an understanding of how ion implantation can be used to modify materials for subsequent removal. While not directly about gate structures, it highlights the use of implantation to alter material properties for processing.
   • H. Seidel et al. (Non-Patent Citation): This non-patent literature explicitly discusses the "Influence of Dopants" on the anisotropic etching of crystalline silicon in alkaline solutions. It clearly establishes that the etching rate of polysilicon doped with N-type dopants is higher than undoped polysilicon, and increases with dopant concentration. This is a direct teaching of the mechanism utilized in US8076735 to create the varied trench widths.
   • Motivation and Expectation of Success: A PHOSITA, aware of the issues with metal fill in narrow trenches in gate-last processes, would be motivated to find ways to create wider trench openings. Knowing from Seidel et al. that N-type dopants can significantly increase polysilicon etch rates, and understanding from Intel (or general knowledge) that implantation can selectively introduce dopants, it would be obvious to apply an N-type dopant in a controlled manner to a polysilicon dummy gate layer. By controlling the dopant concentration profile (e.g., higher concentration where a narrower neck is desired, or vice versa depending on the etch chemistry), one could engineer a dummy pattern that, upon removal, yields a trench with a wider top opening. The expectation of success is high given the explicit teachings regarding dopant-dependent etching rates in the Seidel paper.

The invention's specific claim details, such as the ratio of heights (2:1, Claim 2) or the included angle (>90°, Claim 3), might be considered optimization choices for a PHOSITA once the underlying principle of creating a wider-top trench via dopant-controlled etching of a dummy gate is established. These specific dimensions would be within the purview of a PHOSITA experimenting to achieve optimal void-free metal fill, especially given the various teachings on tapered and re-entrant gate structures in the cited prior art.