Prior art

The most relevant prior art for US patent 7923764, based on a review of its cited patents, is identified as US6677209B2. This assessment is based on the patent's abstract describing a key structural feature that closely aligns with the independent claims of US7923764.

Most Relevant Prior Art: US6677209B2

• Full Citation: US6677209B2, "Transistor and manufacturing method thereof", issued January 13, 2004, to Hongo et al., and assigned to Matsushita Electric Industrial Co., Ltd.

• Publication/Filing Date: Issued January 13, 2004. The filing date for this patent (from Google Patents) is August 19, 2002 (U.S. Application No. 10/222,940).

• Brief Description: This patent describes a transistor structure featuring a gate insulating film that includes a high-k dielectric film. A notable characteristic of this gate insulating film is that the portion located under the gate electrode is thicker than the portion located under the sidewall spacers. The patent also details a manufacturing method for this transistor, which involves forming the gate insulating film and gate electrode, and then performing an etching process to thin a portion of the gate insulating film. This design aims to achieve high driving performance and reliability by addressing issues such as breakdown voltage reduction, parasitic capacitance, and short channel effects.

• Claims Potentially Anticipated under 35 U.S.C. § 102:

  • Claim 1 (Device Claim): US6677209B2 directly describes a structure where a high dielectric constant gate insulating film is present under both the gate electrode and the sidewall spacers, and the portion under the gate electrode is thicker than the portion under the sidewall spacers. This explicitly anticipates the core features of Claim 1 of US7923764, which states that the high dielectric constant gate insulating film "is continuously formed so as to extend from under the gate electrode to under the insulating sidewall, and at least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode."

  • Claim 61 (Method Claim): US6677209B2's abstract mentions a "manufacturing method thereof" and specifically notes that the described structure "is formed by using a method... in which a gate insulating film and a gate electrode are formed on a semiconductor substrate, and then an etching process is performed to thin a portion of the gate insulating film". This aligns with the key steps of Claim 61 of US7923764, particularly the step of "etching... part of the high dielectric constant gate insulating film located in an external side to the gate electrode to reduce a thickness of the part". Therefore, US6677209B2 appears to anticipate Claim 61.

  • Other Claims (Dependent Claims): While US6677209B2 broadly anticipates the fundamental device structure (Claim 1) and method (Claim 61) of US7923764, its abstract does not provide specific details that would directly anticipate the nuanced features of the dependent claims, such as:

    • The specific configurations of double sidewalls (Claims 2-6).
    • The presence of a "notch at a side end portion" of the high-k film (Claims 7-12).
    • The explicit inclusion of a "buffer insulating film between the substrate and the high dielectric constant gate insulating film" (Claims 13-24), although a multi-layer gate insulating film is generally contemplated.
    • The use of a "fully silicided gate electrode" (Claims 37-60).
    • Specific processing steps for double sidewalls, wet etching, or full silicidation described in dependent method claims (Claims 62-77).

  However, the existence of US6677209B2 could render many of these dependent claims obvious under 35 U.S.C. § 103, especially if the additional features were known in the art or simple optimizations.