Obviousness

Obviousness Analysis of US Patent 7,923,764 Under 35 U.S.C. § 103

This analysis assesses the obviousness of US Patent 7,923,764 ("the '764 patent") by considering combinations of prior art references and the motivations a person having ordinary skill in the art (POSITA) would have had to combine them, with a reasonable expectation of success. The '764 patent claims semiconductor devices (specifically MISFETs) and methods for fabricating them, focusing on the gate insulating film structure.

Summary of the '764 Patent's Key Claimed Features

The core inventive concepts of the '764 patent, as described in the "SUMMARY OF THE INVENTION" and detailed embodiments, relate to a high dielectric constant (high-k) gate insulating film in a MISFET structure. The key features include:

1. Continuity of High-K Film Under Sidewall(s): The high-k gate insulating film is continuously formed to extend from under the gate electrode to under the insulating sidewall(s). This aims to prevent the side end portions of the high-k film from being in direct contact with the sidewalls, thereby suppressing degradation of its dielectric constant and insulation property.
2. Reduced Thickness Under Sidewall(s): At least part of the high-k gate insulating film located under the insulating sidewall(s) has a smaller thickness than the part under the gate electrode. This "convex shape" (or "double convex shape" for multiple sidewalls) aims to suppress increased capacitance between the gate and drain and adverse effects on circuit speed, while also facilitating ion implantation for extension/LDD regions.

The patent also describes variations such as:

• A double sidewall structure (offset sidewall and outer sidewall).
• The high-k film existing only under the first (offset) sidewall or under both, with different thickness profiles.
• A notch at the side end portion of the high-k film.
• A buffer insulating film (e.g., silicon oxide or oxynitride) between the substrate and the high-k gate insulating film.
• A fully silicided (FUSI) gate electrode.

Identified Prior Art

The '764 patent explicitly acknowledges the following prior art:

• FIGS. 16A and 16B (Ken Watanabe, "HfSiON - CMOS technology for achieving high performance and high reliability," Semi. Forum Japan, 2005): These figures illustrate structures of known MISFETs using a high dielectric constant gate insulating film.

  • FIG. 16A shows a single sidewall structure with a gate electrode (105) on a high-k gate insulating film (104), and an insulating sidewall (107) on its sides. Extension regions (110) are under the sidewall.
  • FIG. 16B shows a double sidewall structure, adding an insulating offset sidewall (106) between the gate electrode (105) and the outer sidewall (107).
  • The '764 patent states that in these known structures, "side end portions of the high dielectric constant gate insulating film are in direct contact with sidewalls," leading to degradation of the high-k film.

• H. Sayama et al., "IEDM Tech. Dig., 2000, p. 239": This reference is cited as disclosing a "double sidewall type MISFET in which an overlapping amount between a gate electrode and an extension region can be optimized in a simple manner."

Obviousness Arguments

A POSITA in semiconductor device fabrication, at the time of the invention (priority date 2005-08-05), would have been motivated to combine features from the cited prior art and general knowledge in the field to arrive at the claimed invention, with a reasonable expectation of success.

Combination 1: Watanabe (FIGS. 16A/16B) + Motivation to Address Known High-K/Sidewall Degradation + Motivation to Control Parasitic Capacitance and Ion Implantation Depth

Rationale:
The '764 patent clearly identifies two significant problems with the existing high-k MISFET structures, such as those shown in Watanabe (FIGS. 16A and 16B):

1. Degradation of High-K Film: The direct contact between the side end portions of the high-k gate insulating film and the sidewalls leads to a "reduction in the dielectric constant and insulation property," deteriorating device characteristics and reliability. This was a recognized issue in the art of integrating high-k dielectrics. A POSITA would be motivated to protect the sensitive high-k material from degradation during subsequent processing, such as sidewall formation. Extending the high-k film to continuously cover the area under the sidewall, as taught by the '764 patent, would be an obvious modification to prevent its exposed edge from direct interaction with the sidewall material, thereby maintaining its integrity. The inventors themselves "have devised a MISFET structure in which a high dielectric constant gate insulating film is kept remaining under sidewalls to prevent end portions of the high dielectric constant gate insulating film from being in contact with the sidewalls, and a method for forming the MISFET structure."

2. Increased Parasitic Capacitance and Ion Implantation Issues: If the high-k film is simply extended under the sidewalls with uniform thickness, it leads to "a capacitance between gate/drain regions is increased, thus resulting in adverse effects on circuit speed." Furthermore, performing extension or LDD implantation through a thick high-k film is problematic due to the heavy metal content and small projection range (Rp) of implanted ions, necessitating increased acceleration energy and resulting in deeper junctions than desired.

   • Faced with the problem of increased capacitance and implantation issues after addressing high-k film degradation by extending it under the sidewalls, a POSITA would be strongly motivated to reduce the thickness of the high-k film in these peripheral regions. This is a common design trade-off: maintaining a thicker high-k film under the gate for strong gate control, while thinning it in the extension regions to minimize parasitic capacitance and enable shallower, more precise dopant profiles for improved short-channel effects. The patent explicitly states this motivation: "To cope with this problem, the inventors have devised a MISFET structure in which a high dielectric constant gate insulating film is kept remaining under sidewalls and part of the high dielectric constant gate insulating film located under the sidewalls is made to have a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under a gate electrode, and a method for forming the MISFET structure."

Therefore, combining the basic MISFET structures of Watanabe (FIGS. 16A or 16B) with the known problems in high-k integration and the conventional approaches to manage parasitic capacitance and ion implantation would lead a POSITA to the claimed structure where the high-k film is continuous under the sidewall(s) but with a reduced thickness in those regions. The manufacturing methods for achieving such stepped or reduced thickness profiles (e.g., selective etching) were also known in the art.

Combination 2: Watanabe (FIGS. 16A/16B) + Known Techniques for Interface Improvement (Buffer Layers)

Rationale:
The '764 patent describes an embodiment (Fourth Embodiment, FIG. 9) where a buffer insulating film (e.g., silicon oxide or oxynitride film 25) is provided between the substrate (1) and the high-k gate insulating film (4A). The patent states this improves the interface between the substrate and the gate insulating film, suppressing deterioration.

• The use of buffer layers, such as SiO2 or SiON, between a silicon substrate and a high-k dielectric film was a well-established technique in semiconductor manufacturing by 2005 to improve interface quality, reduce interface trap densities, and enhance carrier mobility. This was common knowledge for a POSITA working with high-k gate dielectrics.
• Therefore, integrating a known buffer layer between the substrate and the high-k gate insulating film of a Watanabe-type MISFET, regardless of whether the high-k film itself has a continuous and stepped profile, would be an obvious design choice for a POSITA seeking to improve device reliability and performance. The '764 patent acknowledges this, stating that applying a buffer layer to the first, second, or third embodiments would achieve the "same effects."

Combination 3: Watanabe (FIGS. 16A/16B) + Motivation for Performance Optimization (Notches, FUSI Gates)

Rationale:
The '764 patent introduces additional features like notches (e.g., FIG. 6, 7, 8, 10) in the side end portions of the high-k film and fully silicided (FUSI) gate electrodes.

• Notches: The patent states that the notch (20) further suppresses adverse effects on circuit speed due to increased capacitance. If the primary solution of a thinned high-k under the sidewall still presented some parasitic capacitance issues, further removal of the high-k material at the very edge (creating a notch) would be an obvious refinement for a POSITA aiming to minimize parasitic capacitance, as described in the modified example of the first embodiment.
• FUSI Gates: The eighth embodiment describes a FUSI gate electrode (16) to replace a conventional polysilicon gate. FUSI technology was known to offer advantages such as lower gate resistance, improved work function control, and better compatibility with high-k dielectrics. Applying FUSI technology to the gate electrode of a MISFET structure (like those of Watanabe, or the improved structures of the earlier embodiments of '764) would be an obvious design choice for a POSITA seeking to enhance gate performance and reduce overall device resistance.

Conclusion

The primary claims of US7923764, relating to the continuous, yet thickness-reduced, high-k gate insulating film under the sidewall(s), address known problems in high-k MISFET technology that a POSITA would have been motivated to solve. The identified problems (high-k degradation at sidewall interface, increased parasitic capacitance, and ion implantation challenges) and the proposed solutions (continuous, thinned high-k film, buffer layers, notches, FUSI gates) are presented by the patent itself as logical responses to these known issues. Therefore, the combination of basic MISFET structures (Watanabe, Sayama) with common knowledge regarding high-k material integrity, parasitic capacitance management, ion implantation control, interface engineering, and gate electrode optimization would render the claimed invention obvious under 35 U.S.C. § 103.