Prior art

The most relevant prior art for US patent 7920018, as identified from its own citations, is analyzed below. The priority date for US7920018 is January 17, 2007. Therefore, any patent with a priority date before this is relevant for anticipation under 35 U.S.C. § 102.

Analysis of Cited Prior Art

The US patent 7920018 explicitly mentions several prior art patents in its "BACKGROUND OF THE INVENTION" section as disclosing "a known booster circuit employing a triple-well structure switching element". These, along with other cited references, are detailed below.

1. US6100557A

   • Full Citation: US6100557A, "Triple well charge pump," Macronix International Co., Ltd., published August 8, 2000.
   • Publication/Filing Date: Priority date: October 10, 1996; Publication date: August 8, 2000.
   • Brief Description: This patent describes a triple-well charge pump circuit. According to US7920018, it generally discloses a booster circuit employing a triple-well structure switching element.
   • Potential Anticipation (35 U.S.C. § 102): US6100557A likely anticipates elements of Claims 1 and 12 of US7920018 related to a "booster circuit" and "at least one switching element in either or both of the first well region and the second well region" for transferring charges, particularly in the context of a triple-well structure. Claims 1 and 12 are distinguished by the use of an analog comparison circuit to compare potentials between two boosting cell rows and applying the resultant well bias potential, which is not directly evident from the title or general description of US6100557A.

2. US6121821A

   • Full Citation: US6121821A, "Booster circuit for semiconductor device," Nec Corporation, published September 19, 2000.
   • Publication/Filing Date: Priority date: March 31, 1998; Publication date: September 19, 2000.
   • Brief Description: This patent describes a booster circuit for a semiconductor device. US7920018 states it discloses a booster circuit employing a triple-well structure switching element.
   • Potential Anticipation (35 U.S.C. § 102): Similar to US6100557A, US6121821A likely anticipates the basic concepts of a "booster circuit" and a "switching element" within a triple-well structure as broadly recited in Claims 1 and 12 of US7920018. However, it does not appear to disclose the specific comparison and well bias control across two rows of cells as claimed in US7920018.

3. US7102422B1

   • Full Citation: US7102422B1, "Semiconductor booster circuit having cascaded MOS transistors," Nippon Steel Corporation, published September 5, 2006.
   • Publication/Filing Date: Priority date: April 20, 1994; Publication date: September 5, 2006.
   • Brief Description: This patent describes a semiconductor booster circuit with cascaded MOS transistors. US7920018 indicates it discloses a booster circuit employing a triple-well structure switching element.
   • Potential Anticipation (35 U.S.C. § 102): US7102422B1 likely anticipates the general configuration of a "booster circuit" with "switching elements" and potentially a "triple-well structure" as foundational elements of Claims 1 and 12 of US7920018. The specific inventive aspects of US7920018 regarding analog comparison and shared well regions are not indicated by the title or general context.

4. US6501325B1

   • Full Citation: US6501325B1, "Low voltage supply higher efficiency cross-coupled high voltage charge pumps," Cypress Semiconductor Corp., published December 31, 2002.
   • Publication/Filing Date: Priority date: January 18, 2001; Publication date: December 31, 2002.
   • Brief Description: This patent describes high-efficiency cross-coupled high-voltage charge pumps suitable for low voltage supplies.
   • Potential Anticipation (35 U.S.C. § 102): This patent's focus on high-efficiency charge pumps suggests it deals with similar problems of boosting voltage. While it likely anticipates the general concept of a "booster circuit" and charge transfer, the specific mechanism of using an analog comparison circuit to control well bias potentials between two distinct boosting cell rows, as claimed in US7920018, would need to be thoroughly examined to determine anticipation.

5. US6734717B2

   • Full Citation: US6734717B2, "Charge pump circuit," Hynix Semiconductor Inc., published May 11, 2004.
   • Publication/Filing Date: Priority date: December 29, 2001; Publication date: May 11, 2004.
   • Brief Description: This patent broadly describes a charge pump circuit.
   • Potential Anticipation (35 U.S.C. § 102): As a general "charge pump circuit," it would anticipate the fundamental concept of a "booster circuit" and charge transfer elements. Without further details, it's difficult to assess anticipation of the specific well bias control and dual-row comparison features of US7920018's Claims 1 and 12.

6. US6878981B2

   • Full Citation: US6878981B2, "Triple-well charge pump stage with no threshold voltage back-bias effect," Tower Semiconductor Ltd., published April 12, 2005.
   • Publication/Filing Date: Priority date: March 20, 2003; Publication date: April 12, 2005.
   • Brief Description: This patent describes a triple-well charge pump stage designed to mitigate the threshold voltage back-bias effect. This aligns with a problem US7920018 aims to solve by suppressing the substrate biasing effect.
   • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant as it specifically addresses the back-bias effect in triple-well charge pumps, a core problem US7920018 seeks to improve upon. It likely anticipates the "triple-well structure," "switching element," and the goal of suppressing the "substrate biasing effect" mentioned in Claims 1 and 12 and their associated advantages. The distinguishing feature for US7920018 would be its specific use of an analog comparison circuit comparing potentials from two rows of cells to generate and apply a well bias potential.

7. US6888400B2

   • Full Citation: US6888400B2, "Charge pump circuit without body effects," Ememory Technology Inc., published May 3, 2005.
   • Publication/Filing Date: Priority date: August 9, 2002; Publication date: May 3, 2005.
   • Brief Description: This patent describes a charge pump circuit designed to operate without body effects, which is another term related to the substrate biasing effect.
   • Potential Anticipation (35 U.S.C. § 102): Similar to US6878981B2, this patent directly addresses the "body effect" (substrate biasing effect) in charge pumps, which is a problem US7920018 also aims to mitigate. It would therefore anticipate elements related to suppressing the substrate biasing effect and the components of a charge pump. The novelty of US7920018 would rest on the specific analog comparison circuit and its application to well bias across multiple boosting cell rows.

8. US6952129B2

   • Full Citation: US6952129B2, "Four-phase dual pumping circuit," Ememory Technology Inc., published October 4, 2005.
   • Publication/Filing Date: Priority date: January 12, 2004; Publication date: October 4, 2005.
   • Brief Description: This patent describes a charge pump circuit utilizing a four-phase dual pumping scheme.
   • Potential Anticipation (35 U.S.C. § 102): This patent describes a specific type of charge pump ("dual pumping circuit") that implies multiple stages or rows. While it might anticipate the concept of multiple boosting cell rows and charge transfer, the "four-phase" clocking is different from the two-phase example primarily discussed in US7920018 (though US7920018 also mentions four-phase). The critical distinction for US7920018's claims would still be the analog comparison circuit's function in generating and applying the well bias potential between rows.

9. US7123077B2

   • Full Citation: US7123077B2, "Four-phase charge pump circuit with reduced body effect," Ememory Technology Inc., published October 17, 2006.
   • Publication/Filing Date: Priority date: August 3, 2004; Publication date: October 17, 2006.
   • Brief Description: This patent describes a four-phase charge pump circuit that explicitly aims to reduce the body effect.
   • Potential Anticipation (35 U.S.C. § 102): This patent is highly relevant as it combines "four-phase charge pump" with "reduced body effect," directly addressing both the pump architecture and the substrate biasing issue that US7920018 seeks to improve. It would anticipate elements related to booster circuits, switching elements, and methods to mitigate body effects. The specific analog comparison circuit approach of US7920018, particularly the comparison between two rows for well bias, would be the differentiating factor.

10. US20070096796A1

    • Full Citation: US20070096796A1, "High voltage charge pump with wide range of supply voltage," Firmansyah Teezar R, published May 3, 2007.
    • Publication/Filing Date: Priority date: August 26, 2005; Publication date: May 3, 2007.
    • Brief Description: This patent application describes a high-voltage charge pump capable of operating over a wide range of supply voltages.
    • Potential Anticipation (35 U.S.C. § 102): This patent generally describes a charge pump for high voltage, which relates to the overall function of US7920018. However, its title doesn't suggest the specific well biasing control or dual-row comparison feature. It would broadly anticipate the "booster circuit" aspect.

11. US7317347B2

    • Full Citation: US7317347B2, "Charge pump circuit with reuse of accumulated electrical charge," Stmicroelectronics S.R.L., published January 8, 2008.
    • Publication/Filing Date: Priority date: November 22, 2004; Publication date: January 8, 2008.
    • Brief Description: This patent describes a charge pump circuit that focuses on the reuse of accumulated electrical charge to improve efficiency.
    • Potential Anticipation (35 U.S.C. § 102): This patent addresses efficiency in charge pumps, which is a goal of US7920018. It might anticipate aspects of charge transfer and improving boost efficiency. However, it does not explicitly disclose the unique well biasing control method of US7920018's Claims 1 and 12.

12. US7532062B2

    • Full Citation: US7532062B2, "Semiconductor charge pump using MOS (metal oxide semiconductor) transistor for current rectifier device," Kabusiki Kaisha Toshiba, published May 12, 2009.
    • Publication/Filing Date: Priority date: November 8, 2005; Publication date: May 12, 2009.
    • Brief Description: This patent describes a semiconductor charge pump that uses MOS transistors as current rectifier devices.
    • Potential Anticipation (35 U.S.C. § 102): This patent addresses the use of MOS transistors for current rectification in charge pumps, which are a form of switching elements in booster circuits. It would therefore anticipate aspects of the "switching element" and "booster circuit" components of US7920018. The specific analog comparison and dual-row well bias control of US7920018's claims would be the distinguishing features.

Overall Most Relevant Prior Art:

The most relevant prior art appears to be US6878981B2 ("Triple-well charge pump stage with no threshold voltage back-bias effect") and US7123077B2 ("Four-phase charge pump circuit with reduced body effect"). These patents directly address the problem of the "substrate biasing effect" or "body effect" in charge pumps employing triple-well structures, which is a primary concern for US7920018. While they disclose booster circuits and methods to mitigate these effects, the unique contribution of US7920018, as recited in Claims 1 and 12, lies in the specific architecture of comparing potentials from two separate boosting cell rows using an analog comparison circuit to generate and apply a well bias potential to the first well region of the switching elements, thereby reducing current consumption and layout area, and improving boost efficiency.