Obviousness

Obviousness Analysis of US Patent 7920018 Under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that could render claims of US Patent 7920018 obvious to a person having ordinary skill in the art (PHOSITA). The focus is on the motivation to combine these references to arrive at the claimed invention, particularly regarding the control of N-well potentials in triple-well structures for improved booster circuit performance.

Background on Prior Art and Obviousness

The present invention (US7920018) relates to a booster circuit employing switching elements with a triple-well structure. A conventional booster circuit (Figure 25 of US7920018) is described, where the P-well and N-well of each charge transfer transistor are connected to the source to suppress the substrate biasing effect. However, this conventional approach suffers from decreased boost efficiency and increased layout area due to the parasitic capacitance of the N-well being charged and discharged by clock signals, and the necessity of separating N-wells for each transistor. The stated object of US7920018 is to provide a booster circuit that suppresses current consumption and layout area while still mitigating the substrate biasing effect.

The listed prior art includes several patents related to booster circuits and triple-well charge pumps, which were known at the time of the invention:

• US6100557A: Triple well charge pump.
• US6121821A: Booster circuit for semiconductor device.
• US7102422B1: Semiconductor booster circuit having cascaded MOS transistors.
• US6501325B1: Low voltage supply higher efficiency cross-coupled high voltage charge pumps.
• US6734717B2: Charge pump circuit.
• US6888400B2: Charge pump circuit without body effects.
• US6878981B2: Triple-well charge pump stage with no threshold voltage back-bias effect.
• US6952129B2: Four-phase dual pumping circuit.
• US7123077B2: Four-phase charge pump circuit with reduced body effect.
• US20070096796A1: High voltage charge pump with wide range of supply voltage.
• US7317347B2: Charge pump circuit with reuse of accumulated electrical charge.
• US7532062B2: Semiconductor charge pump using MOS (metal oxide semiconductor) transistor for current rectifier device.

Combination 1: US6100557A in view of US6878981B2 and the conventional booster circuit (Figure 25 of US7920018)

Claim Elements Addressed: The primary independent claims (Claims 1 and 12) of US7920018 introduce the use of an analog comparison circuit to control the well bias potential of the first well region (N-well) of switching elements in boosting cells arranged in rows. This control aims to reduce current consumption and layout area while maintaining suppression of the substrate biasing effect.

Prior Art Disclosures:

• US6100557A (Triple well charge pump): This patent discloses a triple-well charge pump, addressing the need for boosting circuits in non-volatile memories. It teaches the use of a triple-well structure to improve charge pump efficiency. While it deals with triple-well structures, it doesn't explicitly detail using an analog comparison circuit to dynamically control the N-well potential based on input/output potentials of different stages in multiple rows for the specific purpose of reducing parasitic capacitance and layout area in the manner claimed by US7920018.
• US6878981B2 (Triple-well charge pump stage with no threshold voltage back-bias effect): This reference also focuses on triple-well charge pumps and aims to eliminate the threshold voltage back-bias effect, thereby improving efficiency. It emphasizes connecting the N-well to the source of the switching element, similar to the conventional circuit described in US7920018.
• Conventional Booster Circuit (Figure 25 of US7920018): This figure illustrates a typical triple-well booster circuit where the P-well and N-well of each charge transfer transistor are connected to the source to suppress the substrate biasing effect. However, the applicant of US7920018 identifies a drawback of this conventional approach as the charging/discharging of the N-well's parasitic capacitance, leading to decreased boost efficiency and increased layout area.

Motivation for Combination:
A PHOSITA, aware of the issues with conventional triple-well booster circuits (as described in the background of US7920018 and exemplified by the conventional circuit in Figure 25, which is consistent with the general principles of US6100557A and US6878981B2), would be motivated to find ways to improve efficiency and reduce layout area. The problem explicitly stated in US7920018 is the current consumption and layout area increase due to the parasitic capacitance of the N-well being charged and discharged by clock signals in a conventional triple-well structure where the N-well is connected to the source.

Given the goal of improving boost efficiency and reducing current consumption and layout area, a PHOSITA would seek methods to minimize the voltage swing of the N-well or to share N-well regions. Analog comparison circuits are well-known components for comparing voltage levels and generating control signals. The idea of using an analog comparison circuit to fix or control the N-well potential to either the input or output potential of a boosting cell stage, as proposed in US7920018, directly addresses the problem of N-well parasitic capacitance charging and discharging. By selecting the higher or lower of potentials from corresponding stages in parallel boosting cell rows, the N-well potential could be dynamically adjusted to minimize the voltage difference between the N-well and the substrate, thereby reducing the amount of charge that needs to be moved into and out of the N-well.

Specifically, US6100557A discloses the triple-well structure. US6878981B2 further details how to manage body bias in such structures by connecting the N-well to the source. The problem identified in US7920018 with this approach is the N-well's parasitic capacitance. A PHOSITA, seeking to overcome this problem, would look for ways to stabilize or control the N-well potential more effectively than simply connecting it to the source. An analog comparison circuit, capable of sensing potentials and outputting a specific bias, would be a logical tool to achieve this. The motivation would be to maintain the benefits of suppressing the substrate biasing effect (as taught by US6878981B2 and the conventional circuit) while simultaneously mitigating the disadvantages of N-well parasitic capacitance by actively controlling its potential based on the dynamic voltages within the boosting cell stages, especially in a multi-stage, multi-row configuration. The concept of comparing potentials across different rows and stages to derive an optimal well bias is an engineering choice to optimize the known triple-well structure for efficiency and area.

Therefore, combining the teaching of triple-well charge pumps from US6100557A (or US6878981B2) with the understanding of the N-well parasitic capacitance problem (as explained in US7920018's background) would lead a PHOSITA to employ an analog comparison circuit to provide a more controlled N-well bias, aiming to reduce current consumption and layout area.

Combination 2: US6888400B2 in view of US6121821A and US7123077B2

Claim Elements Addressed: This combination addresses the general concept of reducing body effects in charge pump circuits and extending it to a multi-row configuration with N-well potential control via an analog comparison circuit.

Prior Art Disclosures:

• US6888400B2 (Charge pump circuit without body effects): This patent explicitly aims to provide a charge pump circuit that is free from body effects, using specific transistor arrangements to achieve this. It addresses the fundamental problem of body biasing, which US7920018 also seeks to mitigate.
• US6121821A (Booster circuit for semiconductor device): This reference describes a booster circuit generally, which could include multiple stages or be part of a larger system. While it may not specifically detail triple-well N-well control via analog comparison, it represents the broader field of booster circuit design.
• US7123077B2 (Four-phase charge pump circuit with reduced body effect): This patent, like US6888400B2, focuses on reducing body effects in charge pump circuits, specifically in a four-phase configuration. The explicit mention of "reduced body effect" signifies the ongoing effort in the art to overcome this challenge.

Motivation for Combination:
A PHOSITA would be well aware of the limitations imposed by body effects on the performance of charge pump circuits, as evidenced by references like US6888400B2 and US7123077B2, which directly address this issue. The goal of US7920018 to suppress the substrate biasing effect in triple-well structures aligns directly with the objectives of these prior art documents.

Given the existing knowledge of reducing body effects (US6888400B2, US7123077B2) and the general architecture of booster circuits (US6121821A), a PHOSITA would be motivated to apply solutions for body effect reduction to more complex booster circuit designs, such as those with multiple stages and parallel rows. The specific challenge addressed by US7920018 is applying body effect reduction techniques in a way that also reduces current consumption and layout area, particularly when N-wells are involved in triple-well devices.

The analog comparison circuit described in US7920018 offers a means to dynamically control the N-well potential, which is a sophisticated approach to mitigating body effects and parasitic capacitance issues simultaneously. If prior art already teaches reducing body effects and utilizing triple-well structures, then the next logical step for a PHOSITA facing the problems of current consumption and layout area (as described in US7920018) would be to implement a more active and optimized control scheme for the well potentials. An analog comparison circuit is a standard building block for voltage regulation and comparison, making its application to sense and control N-well potentials a design choice driven by known problems and available tools to achieve improved efficiency and smaller footprint.

For instance, US6888400B2 describes a charge pump without body effects. If a PHOSITA were to implement this in a multi-stage, multi-row booster circuit (as generally understood from the field of US6121821A), and encountered the N-well parasitic capacitance issue described in US7920018, they would seek methods to further optimize. Dynamically choosing the higher or lower potential of adjacent stages/rows via an analog comparator to bias the N-well would be an obvious design choice to minimize voltage swings across the N-well junction and reduce the associated charging/discharging current and thus current consumption, while also enabling sharing of N-well regions to reduce layout area.

Conclusion on Obviousness

The core inventive step of US7920018 lies in using an analog comparison circuit to dynamically control the N-well potential of switching elements in a triple-well structure within a multi-row booster circuit, specifically to reduce parasitic capacitance effects, current consumption, and layout area.

While individual elements like triple-well structures, body effect reduction techniques, and analog comparison circuits were known in the prior art, the specific combination and the explicit motivation to solve the N-well parasitic capacitance and layout area problem in multi-row booster circuits using an analog comparison circuit for dynamic N-well biasing could be argued as non-obvious.

However, a PHOSITA would have been motivated to combine these known elements to address the acknowledged problems in existing booster circuit designs. The desire to improve efficiency (reduce current consumption) and reduce physical footprint (layout area) are common driving forces in semiconductor circuit design. Given the recognition of N-well parasitic capacitance as a source of inefficiency and increased area in conventional triple-well booster circuits, and the availability of analog comparison circuits for voltage control, a PHOSITA would likely consider solutions that involve actively managing well potentials. The selection of the higher or lower potential of adjacent stages/rows to bias the N-well of switching elements would represent an engineering optimization based on known circuit behaviors and components, aimed at directly mitigating the identified problems.

Therefore, while the specific implementation detailed in US7920018 offers advantages, the underlying principle of using an analog comparison circuit to dynamically control N-well potentials in triple-well devices within a multi-stage, multi-row booster circuit to improve efficiency and reduce area could be considered obvious to a PHOSITA. The combination of prior art focusing on triple-well structures (US6100557A, US6878981B2), body effect reduction (US6888400B2, US7123077B2), and general booster circuit design (US6121821A) would provide sufficient motivation and means for a PHOSITA to arrive at the claimed invention, particularly given the explicit problem statement provided in US7920018 itself regarding the shortcomings of prior art solutions.