Prior art

The following analysis identifies the most relevant prior art for US Patent 7888195, "Metal gate transistor and method for fabricating the same," based on the citations provided within the patent document. The prior art is assessed for potential anticipation under 35 U.S.C. § 102, noting the limitations of evaluating anticipation solely from titles and publication/priority dates.

US Patent 7888195 has a filing date and priority date of August 26, 2008.

Most Relevant Prior Art for US7888195

From the cited references within US7888195, US20060065939A1 is the most relevant.

• Full Citation: US20060065939A1, Doczy Mark L et al., "Metal gate electrode semiconductor device"
• Publication Date: March 30, 2006. (Priority Date: September 27, 2004)
• Brief Description: This patent application describes a semiconductor device incorporating a metal gate electrode. The title directly addresses the core subject matter of US7888195, which is a metal gate transistor and its fabrication.
• Potential Anticipation: Given its title, US20060065939A1 is highly likely to disclose fundamental aspects of metal gate transistors. If it describes a gate-last (replacement gate) fabrication process, the use of high-k dielectric materials, or techniques for adjusting the work function of metal gates for different transistor types (e.g., NMOS and PMOS), it could potentially anticipate several claims of US7888195. Specifically, it could anticipate the foundational steps of forming a metal gate transistor and the resulting structure, as broadly outlined in independent Claim 1 of US7888195 (method for fabricating a metal gate transistor) and the implied apparatus claims related to the metal gate structure. Without the full text of US20060065939A1, the exact scope of anticipation regarding the specific sequence of cap layer deposition and selective removal as detailed in US7888195's Claim 1 cannot be definitively stated, but the general concept is likely covered.

Other Cited Prior Art

The following documents were also cited, but appear less directly relevant to the specific inventive aspects of US7888195 based on their titles.

1. US20040159903A1

   • Full Citation: US20040159903A1, Burgener Robert H. et al., "Compounds and solid state apparatus having electroluminescent properties"
   • Publication Date: August 19, 2004. (Priority Date: February 14, 2003)
   • Brief Description: This patent application is directed to compounds and solid-state apparatuses exhibiting electroluminescent properties.
   • Potential Anticipation: This reference pertains to electroluminescent devices, a different technological field from metal gate transistor fabrication. It is unlikely to anticipate any claims of US7888195, which focuses on semiconductor device manufacturing for transistors.

2. US20040173886A1

   • Full Citation: US20040173886A1, Carley L. Richard, "Micromachined assembly with a multi-layer cap defining a cavity"
   • Publication Date: September 9, 2004. (Priority Date: March 7, 2003)
   • Brief Description: This patent application describes a micromachined assembly that includes a multi-layer cap for defining a cavity.
   • Potential Anticipation: This reference relates to micro-electromechanical systems (MEMS) or general micro-fabrication techniques for creating cavities. Its subject matter is distinct from the specific processes and structures involved in fabricating metal gate transistors, making it unlikely to anticipate claims of US7888195.

3. US20050263829A1

   • Full Citation: US20050263829A1, Yoon-Jong Song, "Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same"
   • Publication Date: December 1, 2005. (Priority Date: May 27, 2004)
   • Brief Description: This patent application focuses on semiconductor devices that feature phase change memory cells and their manufacturing methods.
   • Potential Anticipation: While it deals with semiconductor devices and fabrication methods, its specific emphasis on "phase change memory cells" suggests a different device architecture and potentially different fabrication steps compared to the metal gate transistors for logic applications described in US7888195. General semiconductor manufacturing steps might overlap, but the specific innovations of US7888195 regarding high-k dielectrics and selective work function engineering for logic transistors are not clearly indicated by the title to be anticipated.

4. US20060134433A1

   • Full Citation: US20060134433A1, Planar Systems Oy, "Multilayer material and method of preparing same"
   • Publication Date: June 22, 2006. (Priority Date: December 21, 2004)
   • Brief Description: This patent application describes a multilayer material and a method for its preparation.
   • Potential Anticipation: The title is very broad and does not specify application to semiconductor devices, transistors, or metal gates. While transistor fabrication involves multiple layers, this reference is too general to anticipate the specific structural or method claims of US7888195, which are focused on the unique aspects of metal gate transistor fabrication.

5. US20090017563A1

   • Full Citation: US20090017563A1, Texas Instruments Incorporated, "Plasma treatment and repair processes for reducing sidewall damage in low-k dielectrics"
   • Publication Date: January 15, 2009. (Priority Date: July 11, 2007)
   • Brief Description: This patent application details plasma treatment and repair processes aimed at reducing sidewall damage in low-k dielectric materials.
   • Potential Anticipation: Although its priority date (July 11, 2007) predates the filing date of US7888195, the subject matter of this reference is specific to plasma treatment and repair processes for low-k dielectrics. US7888195's invention focuses on the formation of metal gates, high-k dielectrics, and selective work function layers, not specifically on damage repair in low-k dielectrics. Therefore, it is unlikely to anticipate the specific method or structural claims of US7888195.