Obviousness

US patent 7888195 describes a method for fabricating metal gate transistors, particularly emphasizing a "gate-last" or "replacement gate" process to achieve different work functions for NMOS and PMOS devices within a CMOS structure. The core innovation, as outlined in claim 1, involves forming dummy gates, removing them to create openings, depositing a high-k dielectric layer, and then selectively depositing and removing a first cap layer to tailor the work function before depositing the final metal layer.

The following analysis considers prior art references cited within US7888195 and their relevance to an obviousness determination under 35 U.S.C. § 103, particularly focusing on the combination of references US20060065939A1 (Doczy) and US8178902B2 (Infineon).

I. Prior Art References

1. US20060065939A1 (Doczy): "Metal gate electrode semiconductor device"

   • Publication Date: March 30, 2006
   • Relevant Disclosure: Doczy describes a method for forming metal gate electrodes in semiconductor devices using a gate-last approach. It teaches the replacement of a dummy gate with a high-k dielectric layer and a metal gate. Crucially, Doczy acknowledges the need for different work function metals for NMOS and PMOS transistors in a CMOS integrated circuit and discusses methods to achieve these different work functions through selective deposition or etching of various layers.

2. US8178902B2 (Infineon): "CMOS transistor with dual high-k gate dielectric and method of manufacture thereof"

   • Priority Date: June 17, 2004 (predates US7888195's priority date of August 26, 2008)
   • Relevant Disclosure: Infineon describes CMOS devices utilizing a gate-last process to integrate high-k dielectrics and achieve varying threshold voltages for NMOS and PMOS transistors. This patent explicitly teaches the deposition of a "work function tuning layer" or "cap layer" on the high-k dielectric. It then details the selective removal of portions of this tuning layer from one type of transistor region (e.g., PMOS) to achieve different effective work functions for the NMOS and PMOS devices. After this selective removal, a common metal gate material is deposited.

II. Obviousness Analysis of US7888195 (Claim 1)

Claim 1 of US7888195 recites a method for fabricating a metal gate transistor comprising:

• providing a substrate having a first transistor region and a second transistor region;
• forming a plurality of dummy gates on the substrate;
• forming a source/drain region at two sides of each dummy gate;
• forming a dielectric layer to cover the dummy gates;
• removing the dummy gates to form a plurality of openings;
• forming a high-k dielectric layer to cover the dielectric layer and surface of each opening;
• depositing a first cap layer on the high-k dielectric layer;
• removing the first cap layer disposed in the second transistor region; and
• forming a metal layer on the first cap layer of the first transistor region and the high-k dielectric layer of the second transistor region.

Combination of Doczy (US20060065939A1) and Infineon (US8178902B2):

A person having ordinary skill in the art (PHOSITA) at the time of the invention of US7888195 would have found the method of claim 1 obvious when considering the combined teachings of Doczy and Infineon.

Motivation for Combination:

The motivation to combine these references stems from several well-understood challenges and common solutions in semiconductor manufacturing:

1. Addressing the Polysilicon Depletion Effect: Both Doczy and the background of US7888195 identify the problem of the polysilicon depletion effect, which degrades device performance in conventional MOSFETs. The known solution was the adoption of high-k dielectrics and metal gates.
2. Need for Dual Work Functions in CMOS: For CMOS technology, it is crucial to have different gate work functions for NMOS and PMOS devices to achieve desired threshold voltages and optimize device performance. Doczy explicitly recognizes this requirement.
3. Gate-Last Process as an Enabler: The gate-last (or replacement gate) approach was a well-established technique for integrating advanced gate stacks, including high-k dielectrics and metal gates, as it alleviates thermal budget issues. Both Doczy and Infineon utilize this foundational process.

Mapping Claim Elements to the Combination:

• Substrate, dummy gates, source/drain regions, covering dielectric layer, and removing dummy gates to form openings: These steps are broadly taught by Doczy as part of a conventional gate-last process for forming metal gate transistors. Infineon also explicitly describes the use of dummy gates in a gate-last process.
• Forming a high-k dielectric layer in the openings: Doczy teaches forming high-k dielectric layers as part of the replacement gate process. Infineon similarly teaches forming a high-k dielectric layer within the gate trench.
• Depositing a first cap layer on the high-k dielectric layer and removing the first cap layer disposed in the second transistor region: This specific sequence for achieving differential work functions is explicitly taught by Infineon. Infineon discloses depositing a "work function tuning layer" (equivalent to the "cap layer" in US7888195) on the high-k dielectric and then selectively removing it from one type of transistor region (e.g., PMOS) before further processing.
• Forming a metal layer on the first cap layer of the first transistor region and the high-k dielectric layer of the second transistor region: Following the selective removal step taught by Infineon, the subsequent deposition of a metal layer would naturally result in the metal layer contacting the remaining cap layer in the first region and the high-k dielectric directly in the second region, thereby creating the desired differential work functions. Doczy generally teaches the formation of metal gates after high-k dielectric.

Therefore, a PHOSITA, faced with the known challenge of fabricating high-performance CMOS devices with metal gates and dual work functions via a gate-last process (as understood from Doczy), would have turned to techniques for work function engineering. Infineon directly provides a solution to this problem by detailing the use of a selectively removed cap layer. Combining these teachings would lead directly to the method described in claim 1 of US7888195, thereby rendering it obvious.

Dependent claims, such as those specifying NMOS/PMOS regions (claims 2, 4), specific cap layer materials (claims 3, 5, 6), metal layer materials (claim 7), or subsequent planarization and conductive layer fill steps (claims 9, 11), represent routine choices or conventional fabrication steps that would also be obvious to a PHOSITA in light of the combined prior art and general knowledge in the field. The introduction of a second cap layer in the PMOS region (claims 5 and 6) is also explicitly contemplated as an alternative work function tuning method within the specification of US7888195 and would be an obvious design choice for a PHOSITA seeking to further refine work function.