US 7836381

Here's a concise summary of US patent 7836381:

• Patent Number: US7836381B1
• Title: Computer readable medium with instructions for resource sharing in a telecommunications environment
• Inventors: Marcos C. Tzannes and Michael Lund
• Original Assignee: Aware Inc
• Current Assignee: TQ Delta LLC
• Filing Date: August 9, 2010 (Application number US12/853,020)
• Issue Date: November 16, 2010
• Abstract: A transceiver is designed to share memory and processing power among multiple transmitter and/or receiver latency paths in a communication system that supports various applications. For instance, the transceiver's latency paths can share an interleaver/deinterleaver memory. This memory allocation can be determined based on application requirements such as data rate, latency, bit error rate (BER), impulse noise protection, or any other relevant communication system parameter.

Plain-Language Overview of Independent Claims:

• Independent Claim 1: This claim describes a non-transitory computer-readable storage medium containing instructions that, when executed, enable a transceiver to allocate shared memory. The process involves:

  1. The transceiver either sending or receiving a message during initialization that specifies the maximum amount of memory available for an interleaver.
  2. The transceiver determines how much memory the interleaver needs to interleave Reed-Solomon (RS) coded data within a shared memory space.
  3. A specific amount of this shared memory is allocated to the interleaver for transmitting RS coded data at a particular data rate, ensuring this allocation does not exceed the maximum specified in the initial message.
  4. Another portion of the shared memory is allocated to a deinterleaver for deinterleaving RS coded data received at a different data rate.
  5. Finally, the interleaving and deinterleaving operations occur simultaneously using their respective allocated portions of the shared memory.

• Independent Claim 5: This claim is structurally very similar to Claim 1 but focuses on the deinterleaver first. It describes a non-transitory computer-readable storage medium with instructions for allocating shared memory in a transceiver, where:

  1. The transceiver sends or receives a message during initialization indicating the maximum memory available for a deinterleaver.
  2. The transceiver determines the memory needed by the deinterleaver to deinterleave a first set of Reed-Solomon (RS) coded data bytes within a shared memory.
  3. A first number of bytes from the shared memory is allocated to this deinterleaver for deinterleaving data at a specific data rate, not exceeding the maximum limit from the message.
  4. Concurrently, a second number of bytes from the shared memory is allocated to an interleaver for interleaving another set of RS coded data bytes.
  5. Both the deinterleaving and interleaving processes utilize their respective shared memory allocations at the same time.

USPTO and CAFC 2026 Dockets Search Results:

A search for US patent 7836381 indicates that its legal status is "Expired - Lifetime". The patent was anticipated to expire on October 11, 2025, but is currently listed as "Expired - Lifetime".

Regarding litigation, the patent family has been involved in several US District Court cases, specifically in the Delaware Northern District Court (e.g., cases 1:13-cv-02013, 1:14-cv-00954, 1:15-cv-00121, 1:13-cv-01835) and Alabama Northern District Court (case 5:14-cv-01381). There have also been PTAB (Patent Trial and Appeal Board) cases, including IPR2023-00066 (Not Instituted - Procedural) and IPR2022-00665 (Settlement). Additionally, there was a US case filed in the Court of Appeals for the Federal Circuit (case 18-2158). The first worldwide family litigation was filed in 2013.

No specific CAFC 2026 dockets were found for US7836381 directly, but the existing information from Google Patents covers a CAFC case (18-2158) related to the patent family, though it doesn't specify its status as of 2026. Given the patent's "Expired - Lifetime" status, further litigation is unlikely unless related to past infringements or ongoing appeals from previous cases.

US Patent 7836381 has been involved in several litigation cases. As of April 26, 2026, the known litigation includes:

1. TQ Delta, LLC v. ADTRAN, Inc.

   • Plaintiff(s): TQ Delta, LLC
   • Defendant(s): ADTRAN, Inc.
   • Jurisdiction: U.S. District Court, District of Delaware
   • Case Number: 1:14-cv-00954
   • Filing Date: July 2014
   • Outcome/Current Status: Dismissed Without Prejudice on August 26, 2024. All claims and counterclaims were dismissed without a ruling on the merits, with each side bearing its own fees. US7836381B1 was among the 32 patents at issue in this case.

2. Adtran v. TQ Delta, LLC

   • Plaintiff(s): Adtran
   • Defendant(s): TQ Delta, LLC
   • Jurisdiction: U.S. District Court, District of Delaware
   • Case Number: 1:15-cv-00121
   • Filing Date: February 2015
   • Outcome/Current Status: Case Dismissed in August 2024, following the denial of both parties' cross-motions for summary judgment. No damages were awarded. US7836381B1 was among the 37 patents at issue.

3. TQ Delta LLC v. Verizon Services Corp.

   • Plaintiff(s): TQ Delta LLC
   • Defendant(s): Verizon Services Corp.
   • Jurisdiction: District of Delaware
   • Case Number: 1:15-cv-00616
   • Filing Date: July 17, 2015
   • Outcome/Current Status: This case remains active with upcoming events, including a Final Pretrial Conference scheduled for December 8, 2027, and a Jury Trial scheduled for December 13, 2027. The specific involvement of US7836381 in this particular case, beyond it being part of TQ Delta's portfolio, is not explicitly detailed in the provided snippets.

4. TQ Delta, LLC v. Verizon Services Corp.

   • Plaintiff(s): TQ Delta, LLC
   • Defendant(s): Verizon Services Corp.
   • Jurisdiction: District of Colorado
   • Case Number: 1:2022mc00017
   • Filing Date: Document dated December 21, 2022. The exact filing date of the original case is not clear, as "mc" generally refers to miscellaneous civil cases.
   • Outcome/Current Status: Status not fully clear from the provided snippet, which refers to a document filed on December 21, 2022. The specific involvement of US7836381 in this miscellaneous civil action is not explicitly stated.

5. PTAB case IPR2023-00066

   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2023-00066
   • Filing Date: Not explicitly provided in the patent document.
   • Outcome/Current Status: Not Instituted - Procedural.

6. PTAB case IPR2022-00665

   • Jurisdiction: Patent Trial and Appeal Board (PTAB)
   • Case Number: IPR2022-00665
   • Filing Date: Not explicitly provided in the patent document.
   • Outcome/Current Status: Settlement.

While the Google Patents "Family has litigation" section also lists other cases in the Delaware District Court (e.g., 1:13-cv-02013, 1:13-cv-01835) and Alabama Northern District Court (5:14-cv-01381), and a case in the Court of Appeals for the Federal Circuit (18-2158), the provided search results do not explicitly confirm that US7836381 was an asserted patent in those specific matters, nor do they provide complete details for those cases, such as plaintiff(s), defendant(s), or outcomes beyond general jurisdiction and case numbers.

The USPTO Open Data Portal API reports no AIA trial proceedings for US patent 7836381 as of the most recent ingest. However, web searches indicate two PTAB proceedings have been filed against this patent.

Proceedings overview

There are two PTAB proceedings on file for US7836381: one resulted in a procedural non-institution, and the other ended in a settlement. This gives a defendant a moderate defensive posture, as the patent has not undergone a full merits review by the PTAB and one challenge was settled.

IPR2023-00066 — Unified Patents v. TQ Delta LLC

• Type: Inter Partes Review
• Filed: The exact filing date is not publicly available through direct search results, but the case was filed in 2023.
• Status: Not Instituted - Procedural [cite: US7836381B1 - Computer readable medium with instructions for resource sharing in a telecommunications environment - Google Patents]
• Judge panel: Not publicly available through direct search results.
• Petition grounds: Specific claims challenged, prior art, and statutory bases (§ 102 / § 103) are not publicly available through direct search results. As a standard IPR, it would typically challenge claims under 35 U.S.C. §§ 102 and/or 103.
• Institution decision: Denied (procedurally). The precise reasoning for the procedural non-institution is not publicly available without direct access to the PTAB docket. Procedural denials can occur for various reasons, such as issues with the petition itself, timeliness, or Real Party in Interest (RPI) considerations, though the latter was not found to be a factor for Unified Patents in other cases where their RPI status was challenged.
• Final Written Decision (if issued): No Final Written Decision was issued as institution was denied.
• Settlement / termination: The proceeding terminated procedurally without institution.
• Appeal: No appeal was filed given the non-institution.
• Defensive value: This proceeding indicates that Unified Patents challenged the patent but failed to secure institution, potentially due to a procedural flaw rather than a merits-based decision on patentability. Therefore, the patent claims were not reviewed for validity by the PTAB in this instance, leaving open the possibility of a different petitioner raising similar (or new) arguments.

IPR2022-00665 — [Petitioner not specified] v. TQ Delta LLC

• Type: Inter Partes Review
• Filed: The exact filing date and petitioner are not publicly available through direct search results, but the case was filed in 2022.
• Status: Settlement [cite: US7836381B1 - Computer readable medium with instructions for resource sharing in a telecommunications environment - Google Patents]
• Judge panel: Not publicly available through direct search results.
• Petition grounds: Specific claims challenged, prior art, and statutory bases (§ 102 / § 103) are not publicly available through direct search results.
• Institution decision: The outcome of the institution decision (instituted or denied) before settlement is not publicly available.
• Final Written Decision (if issued): No Final Written Decision was issued due to settlement.
• Settlement / termination: The proceeding was terminated due to settlement. The terms of the settlement are confidential.
• Appeal: No appeal was filed due to settlement.
• Defensive value: A settlement typically means the parties resolved their dispute outside of a full PTAB trial. While the details are unknown, it suggests that the petitioner saw value in settling, possibly to avoid the cost of trial or due to an assessment of the patent's strength. For a defendant, this means the claims were not definitively proven unpatentable, but the settlement itself could imply some perceived risk by the patent owner.

Strategic summary

All claims of US7836381 remain UNTESTED by a full PTAB merits review. Neither of the two identified PTAB proceedings resulted in a Final Written Decision on the patentability of the claims. One IPR (IPR2023-00066) was not instituted due to procedural reasons, and the other (IPR2022-00665) ended in a settlement before a final decision could be reached. This means there are no claims that have been canceled or explicitly sustained by the PTAB.

The estoppel landscape is largely open. Since IPR2023-00066 was not instituted, the petitioner (Unified Patents) and its privies would not be barred by § 315(e)(2) from raising any ground they raised or reasonably could have raised, as estoppel typically only applies to claims that are part of a final written decision or a judgment. For IPR2022-00665, the settlement would typically lead to a joint request for termination, and while the statutory estoppel of § 315(e)(2) might not apply if no FWD was issued, contractual estoppel through a confidential settlement agreement could prevent the specific petitioner from re-challenging the patent. For a new defendant, all prior-art grounds remain available for challenge.

The involvement of Unified Patents as a petitioner [cite: US7836381B1 - Computer readable medium with instructions for resource sharing in a telecommunications environment - Google Patents] indicates that the patent has drawn the attention of an entity focused on challenging patents asserted by Non-Practicing Entities (NPEs). The "Not Instituted - Procedural" outcome suggests a potential flaw in the petition itself, rather than a strong affirmation of the patent's validity on the merits.

Recommended next steps

Given that there are no claims invalidated and no active proceedings, a defendant facing assertion of this patent would find that all claims are currently presumed valid. The absence of a PTAB Final Written Decision means that a district court could still be a viable venue for challenging validity.

Consider these options:

• Investigate IPR2023-00066: If the procedural issue for non-institution can be identified, it might reveal opportunities to file a new, technically sound petition with the PTAB.
• Investigate IPR2022-00665 settlement: While the terms are confidential, understanding why a settlement was reached could provide insights into the patent owner's strategy or any weaknesses the prior petitioner identified.
• Conduct new prior art searches: As no claims have been definitively tested at the PTAB, new prior art challenges could be mounted in a fresh IPR.

Inventors

• Marcos C. Tzannes: At the time of filing (2010-08-09, based on application date), he was an inventor for Aware Inc. The patent itself claims priority to a 2004 provisional application, so he was likely with Aware Inc. then as well.
• Michael Lund: Similarly, an inventor for Aware Inc. at the time of filing.

No unusual patterns like inventors departing en masse shortly after filing are readily apparent from the patent record.

Original assignee

The original assignee named on the issued patent US7836381B1 is Aware Inc..

Aware Inc. (NASDAQ: AWRE) is a technology company primarily known for its biometrics software and services. Historically, Aware Inc. was a significant developer of Digital Subscriber Line (DSL) modem technology. Given the patent's subject matter ("resource sharing in a telecommunications environment" for "DSL systems," "modems," "multicarrier transceivers"), it is highly probable that Aware Inc. shipped products embodying the claims during its active period in the DSL market. Aware Inc. is currently an operating company.

Assignment timeline

• 2012-10-17 (executed) / recorded 2012-10-18 — Reel 029279/0471

  • Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST
  • Assignor: AWARE, INC.
  • Assignee: TQ DELTA, LLC
  • Correspondent: D. D. MITCHELL; MITCHELL SILBERBERG & KNUPP LLP; 11377 W OLYMPIC BLVD; LOS ANGELES CA 90064
  • Context: Fire-sale / transfer to potential asserter.

• 2018-09-27 (executed) / recorded 2018-10-10 — Reel 044675/0285

  • Conveyance: SECURITY INTEREST
  • Assignor: TQ DELTA LLC
  • Assignee: DLI LENDING AGENT, LLC
  • Correspondent: MARTHA L ROGERS; KILPATRICK TOWNSEND & STOCKTON LLP; 1100 PEACHTREE STREET, SUITE 2800; ATLANTA GA 30309-4530. This correspondent recurs in this chain.
  • Context: Securitization (patent portfolio used as collateral).

• 2020-12-21 (executed) / recorded 2021-01-04 — Reel 049583/0970

  • Conveyance: AMENDED AND RESTATED INTELLECTUAL PROPERTY SECURITY AGREEMENT
  • Assignor: TQ DELTA LLC
  • Assignee: ALTER DOMUS (US) LLC
  • Correspondent: MARTHA L ROGERS; KILPATRICK TOWNSEND & STOCKTON LLP; 1100 PEACHTREE STREET, SUITE 2800; ATLANTA GA 30309-4530. This correspondent recurs in this chain.
  • Context: Amended securitization agreement.

Timeline diagram

timeline
    title Ownership of US 7836381
    2004 : Priority date
    2010 : Filed by Aware Inc
    2010 : Issued
    2012 : Assigned to TQ Delta LLC
    2018 : Security interest to DLI Lending
    2021 : Security interest to Alter Domus

NPE / troll-pattern signals

1. Shell-entity transfer — present. The patent moved from Aware Inc., an operating company that shipped products, to TQ Delta LLC (Reel 029279/0471, recorded 2012-10-18). TQ Delta LLC does not appear to ship products and is widely identified as a licensing-only entity.
2. Known asserter in the chain — present. TQ Delta LLC is the current recorded owner of the patent (as the subsequent assignments are security interests, not outright ownership transfers) and is listed as a known patent asserter by Unified Patents and RPX. Google Patents also indicates multiple litigation cases involving this patent.
3. Repeat correspondent across the chain — present. Martha L. Rogers of Kilpatrick Townsend & Stockton LLP is listed as the correspondent for both the 2018-10-10 security interest (Reel 044675/0285) and the 2021-01-04 amended security interest (Reel 049583/0970) involving TQ Delta LLC.
4. Cascading transfers — not present. There is a significant time gap between the initial assignment to TQ Delta LLC (2012) and the subsequent security interests (2018, 2021).
5. Pre-litigation transfer — unclear. While TQ Delta LLC is a known asserter, the exact date of the first infringement suit involving this patent is not precisely provided in the prompt's data to compare against the 2012-10-17 assignment execution date. Google Patents shows litigation, but specific filing dates for this patent's first suit are not immediately apparent to definitively make this call.
6. Bankruptcy fire-sale — not present. Aware Inc. is still an operating company and did not file for bankruptcy before assigning the patent to TQ Delta LLC.
7. Privateering — not present. There is no information to suggest that TQ Delta LLC is asserting the patent on behalf of Aware Inc. against its competitors.
8. Defensive aggregator (anti-NPE) — not present. The chain does not terminate at a known defensive aggregator.

Verdict

NPE — high confidence. The patent was transferred from an operating company, Aware Inc., to TQ Delta LLC (Reel 029279/0471, recorded 2012-10-18), which is a known patent asserter identified by Unified Patents and RPX. Furthermore, the patent has been involved in multiple litigations, as indicated by Google Patents.

USPTO Assignment Center search for verification: https://assignmentcenter.uspto.gov/

I have analyzed US patent 7836381 and identified its prior art references from the "Citations" section of the provided patent text. The priority date for US7836381 is October 12, 2004. Any prior art with a priority date before this date is generally relevant for anticipation under 35 U.S.C. § 102.

Here is an analysis of the most relevant prior art cited by US7836381:

Prior Art for US7836381

1. US6337877B1

• Full Citation: US6337877B1: "Method and apparatus for scaling modem transfer capacity in a multi-channel communications system."
• Publication Date: 2002-01-08
• Priority Date: 1998-08-27
• Assignee: Legerity, Inc.
• Brief Description: This patent describes a method and apparatus for scaling modem transfer capacity in a multi-channel communication system, suggesting an awareness of multi-channel communication needs and potentially resource management in such systems.
• Potential Anticipation (35 U.S.C. § 102): This patent's focus on scaling modem transfer capacity in multi-channel systems could potentially anticipate the general concept of managing resources across different communication paths. While it doesn't explicitly mention shared memory for interleavers/deinterleavers, it lays groundwork for multi-channel modem operation which is a prerequisite for US7836381's latency paths. It might generally anticipate the context of allocating resources based on communication needs, which underlies claims 1 and 5 of US7836381.

2. EP1225735A1

• Full Citation: EP1225735A1: "Data communication system."
• Publication Date: 2002-07-24
• Priority Date: 2000-07-07
• Assignee: Matsushita Electric Industrial Co., Ltd.
• Brief Description: This European patent describes a data communication system. Without further detail, its relevance to specific sharing mechanisms for interleavers and deinterleavers is less clear from the title alone.
• Potential Anticipation (35 U.S.C. § 102): The broad title "Data communication system" makes it difficult to pinpoint specific anticipation without reviewing its content. However, depending on its disclosed methods for data handling or resource management in a communication system, it could broadly relate to the environment in which US7836381 operates.

3. EP1246409A1

• Full Citation: EP1246409A1: "Packet retransmission system, packet transmission device, packet reception device, packet retransmission method, packet transmission method and packet reception method."
• Publication Date: 2002-10-02
• Priority Date: 2000-10-05
• Assignee: Mitsubishi Denki Kabushiki Kaisha
• Brief Description: This patent details a packet retransmission system and related devices and methods. Retransmission mechanisms often involve buffering and memory management for packets.
• Potential Anticipation (35 U.S.C. § 102): The focus on packet retransmission implies buffer management and memory usage in transceivers. This could potentially anticipate aspects of shared memory allocation in a general sense, particularly for buffering data that might be subject to interleaving/deinterleaving, which forms a part of US7836381's claims 1 and 5.

4. US20030067877A1

• Full Citation: US20030067877A1: "Communication system and techniques for transmission from source to destination."
• Publication Date: 2003-04-10
• Priority Date: 2001-09-27
• Assignee: Raghupathy Sivakumar
• Brief Description: This publication relates to communication systems and techniques for data transmission.
• Potential Anticipation (35 U.S.C. § 102): Similar to EP1225735A1, the broad title offers limited specific insight into anticipation. However, if it discusses optimization of transmission paths or resource handling, it could touch upon the general problem addressed by US7836381.

5. WO2003063060A2

• Full Citation: WO2003063060A2: "Asymmetric digital subscriber line modem apparatus and methods therefor."
• Publication Date: 2003-07-31
• Priority Date: 2002-01-24
• Assignee: Broadcom Corporation
• Brief Description: This international publication describes ADSL modem apparatus and methods. ADSL systems inherently deal with varying data rates and latency requirements, similar to the context of US7836381.
• Potential Anticipation (35 U.S.C. § 102): Given that US7836381 specifically discusses DSL systems (ADSL, VDSL), this reference on ADSL modems is highly relevant. It could potentially anticipate the use of multiple latency paths, or the need to manage resources for different application requirements (e.g., data rate, latency, BER), as described in claims 1-4 and 5-8, within a DSL context.

6. US6707822B1

• Full Citation: US6707822B1: "Multi-session asymmetric digital subscriber line buffering and scheduling apparatus and method."
• Publication Date: 2004-03-16
• Priority Date: 2000-01-07
• Assignee: Agere Systems Inc.
• Brief Description: This patent directly addresses buffering and scheduling in multi-session ADSL, which is highly relevant to memory management and handling different data streams with varying requirements.
• Potential Anticipation (35 U.S.C. § 102): This patent appears highly relevant as it explicitly discusses "buffering and scheduling" in ADSL. This could directly anticipate the shared memory concept (claims 1 and 5), the allocation based on data rates (claims 1 and 5), and the ability to handle multiple "latency paths" for different applications, even if it doesn't specifically mention "interleaver/deinterleaver memory." The concepts of managing resources for multiple sessions and diverse requirements are central to US7836381.

7. US20040114536A1

• Full Citation: US20040114536A1: "Method for communicating information on fast and slow paths."
• Publication Date: 2004-06-17
• Priority Date: 2002-10-16
• Assignee: O'rourke Aidan
• Brief Description: This publication describes methods for communicating information using "fast and slow paths," which directly relates to the concept of latency paths and different application requirements.
• Potential Anticipation (35 U.S.C. § 102): This reference is very pertinent due to its explicit mention of "fast and slow paths," which directly correlates with the "latency paths" concept of US7836381 used for applications with different latency requirements (e.g., voice vs. video). This could anticipate the fundamental idea of managing multiple paths with different delay characteristics, which is a key driver for shared resource allocation in claims 1-4 and 5-8.

8. US6775320B1

• Full Citation: US6775320B1: "Method and a multi-carrier transceiver supporting dynamic switching between active application sets."
• Publication Date: 2004-08-10
• Priority Date: 1999-03-12
• Assignee: Aware, Inc.
• Brief Description: This patent, from the same original assignee (Aware Inc.) as US7836381, specifically describes multi-carrier transceivers supporting dynamic switching between application sets, and is explicitly mentioned in the background of US7836381 as describing DSL systems supporting multiple applications and FCI blocks (latency paths).
• Potential Anticipation (35 U.S.C. § 102): This is a highly relevant prior art, explicitly cited in the background of US7836381 for describing "DSL systems supporting multiple applications and multiple framer/coder/interleaver FCI blocks (an FCI block is also referred to as a latency path)." It directly anticipates the concept of multiple latency paths, and the need to manage different application requirements, forming the foundation for US7836381's resource sharing. It would likely anticipate the broad setup for allocating resources to multiple latency paths as recited in the preambles of claims 1 and 5, and the general idea of supporting applications with varying data rate, latency, and BER requirements (claims 2-4, 6-8).

9. US6778589B1

• Full Citation: US6778589B1: "Symbol synchronous device and frequency hopping receiver."
• Publication Date: 2004-08-17
• Priority Date: 1998-10-09
• Assignee: Futaba Denshi Kogyo Kabushiki Kaisha
• Brief Description: This patent describes a symbol synchronous device and frequency hopping receiver. It is also explicitly mentioned in the background of US7836381 alongside US6775320B1 as describing DSL systems supporting multiple applications and FCI blocks.
• Potential Anticipation (35 U.S.C. § 102): Similar to US6775320B1, this patent is explicitly cited in the background of US7836381 for describing DSL systems with multiple FCI blocks/latency paths. It therefore broadly anticipates the communication system environment and the existence of multiple latency paths for different applications, as alluded to in the context of claims 1 and 5.

10. US20050180323A1

• Full Citation: US20050180323A1: "System for transmitting high quality speech signals on a voice over Internet protocol network."
• Publication Date: 2005-08-18
• Priority Date: 2004-02-12
• Assignee: Beightol Dean D.
• Brief Description: This publication focuses on transmitting high-quality speech signals over VoIP, implying specific requirements for latency and quality that would necessitate particular resource handling.
• Potential Anticipation (35 U.S.C. § 102): While its publication date is after US7836381's priority date (2004-10-12), its priority date (2004-02-12) is before US7836381's priority date, making it prior art. The specific focus on voice transmission over IP, and ensuring high quality, means it likely addresses latency and error rate requirements, which are factors for allocation in US7836381's claims 2-4 and 6-8. If it discusses memory or processing resource management to meet these QoS (Quality of Service) parameters for voice, it could be highly anticipatory.

11. US20060088054A1

• Full Citation: US20060088054A1: "Resource sharing in a telecommunications environment."
• Publication Date: 2006-04-27
• Priority Date: 2004-10-12
• Assignee: Aware, Inc.
• Brief Description: This is an earlier publication of an application from the same assignee, Aware, Inc., and shares the same priority date as US7836381. It likely describes very similar or identical subject matter regarding resource sharing.
• Potential Anticipation (35 U.S.C. § 102): This is a family member (an earlier publication of a related application) with the same priority date as US7836381. Therefore, it is generally considered part of the same inventive entity and would not typically anticipate under §102 against itself. However, it represents closely related work by the same inventors/assignee. It provides strong evidence of what was known and invented by Aware, Inc. around the priority date, encompassing the core concepts of sharing memory and processing resources, particularly for interleavers/deinterleavers, as claimed in US7836381.

12. US20090300450A1

• Full Citation: US20090300450A1: "Packet retransmission and memory sharing."
• Publication Date: 2009-12-03
• Priority Date: 2006-04-12
• Assignee: Aware, Inc.
• Brief Description: This patent publication from the same assignee focuses on packet retransmission and memory sharing.
• Potential Anticipation (35 U.S.C. § 102): Its priority date (2006-04-12) is after US7836381's priority date (2004-10-12). Therefore, it does not anticipate US7836381 under 35 U.S.C. § 102. It would likely be considered a later development or improvement by the same assignee.

Most Relevant Prior Art Summary:
The most directly relevant prior art appear to be:

• US6775320B1 and US6778589B1: Explicitly mentioned in the background of US7836381 for describing DSL systems with multiple latency paths/FCI blocks, providing the foundational context for the invention.
• US6707822B1: Directly addresses "buffering and scheduling" in multi-session ADSL, which strongly relates to shared memory and allocation based on differing requirements.
• US20040114536A1: Explicitly discusses "fast and slow paths," directly correlating to US7836381's latency paths.
• WO2003063060A2: Addresses ADSL modems, providing the specific communication environment for US7836381.
• US20050180323A1: With a priority date earlier than US7836381, this reference focuses on QoS for voice over IP, which would necessitate management of latency and error rates through resource allocation, thus potentially anticipating the parameter-based allocation in claims 2-4 and 6-8.

These references collectively establish the state of the art concerning multi-path communication, buffering, scheduling, and different QoS requirements within DSL and similar environments prior to US7836381's priority date.

Under 35 U.S.C. § 103, a patent claim is considered obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). The analysis involves identifying a motivation to combine prior art references to arrive at the claimed invention with a reasonable expectation of success.

US Patent 7836381 focuses on sharing memory and processing power among multiple transmitter and/or receiver latency paths in a telecommunications transceiver, particularly in DSL systems. The patent explicitly identifies the challenge it addresses: "a latency path is a complicated digital circuit that requires a large amount of memory and processing power. An interleaver within a latency path can consume a large amount of memory... Likewise, the coding block... consumes a large amount of processing power. In general, as the number of latency paths increase, the memory and processing power requirements for a communication system become larger."

The patent references U.S. Pat. Nos. 6,775,320 and 6,778,589 as background, stating that they "describe DSL systems supporting multiple applications and multiple framer/coder/interleaver FCI blocks (an FCI block is also referred to as a latency path)." These prior art patents teach a system where different applications (e.g., video, voice, internet access) with varying requirements (data rate, latency, bit error rate (BER)) are supported by dedicated latency paths, each typically having its own framer, coder, and interleaver/deinterleaver.

A PHOSITA in the field of telecommunications and computer architecture, at the time of the invention, would have been motivated to combine the teachings of these prior art references with the general knowledge of resource optimization techniques to arrive at the claimed invention.

Combination of Prior Art: U.S. Pat. No. 6,775,320 (or U.S. Pat. No. 6,778,589) and General Knowledge of Resource Sharing in Computing and Telecommunication Systems

Primary Reference: U.S. Pat. No. 6,775,320 (or U.S. Pat. No. 6,778,589)
These patents disclose DSL systems designed to support multiple applications, each requiring different quality-of-service (QoS) parameters such as data rate, latency, and BER. To accommodate these diverse needs, the systems employ multiple dedicated latency paths, with each path including its own framer, coder, and interleaver. This architecture inherently leads to increased memory and processing power demands as more latency paths are added.

Supplemental Prior Art/General Knowledge of a PHOSITA:
A PHOSITA would be well-versed in the principles of resource sharing and dynamic allocation in various computing and communication systems. It is a well-known technique to optimize the use of finite resources, such as memory and processing units, by allowing multiple modules to share a common pool, especially when individual modules do not require their peak resource capacity simultaneously. This reduces overall hardware costs, power consumption, and system complexity. The concept of interleaved memory, for instance, is known in computing to improve throughput by distributing memory access across multiple banks. Furthermore, routine communication between connected transceivers regarding their capabilities and resource availability during initialization or operation (SHOWTIME) is a standard practice in establishing and maintaining efficient communication links.

Motivation to Combine:
The problem explicitly highlighted by US7836381, stemming from the architecture described in U.S. Pat. No. 6,775,320, is the escalating memory and processing requirements due to the dedicated nature of each latency path's interleaver and coder. A PHOSITA, aiming to address this known problem, would be motivated to apply the well-understood principles of resource sharing to reduce the redundant allocation of memory and processing power. This motivation aligns with the "known-techniques" rationale, where a known technique (resource sharing) is applied to improve a device (multi-latency path DSL transceiver) in a predictable way (reduced resource consumption, increased efficiency).

Obviousness Analysis of Independent Claims 1 and 5:

Both independent claims (Claim 1 focusing on interleaver-first allocation, Claim 5 on deinterleaver-first allocation) describe a computer-readable medium with instructions for a method of allocating shared memory in a transceiver. The core elements are:

1. Transmitting/receiving a message during initialization specifying maximum memory: In a DSL system with shared resources, it would be an obvious engineering decision for communicating transceivers to exchange information about their memory capabilities (e.g., maximum shared memory available for interleavers/deinterleavers). This information is crucial for negotiating and configuring compatible system parameters during initialization or SHOWTIME.
2. Determining memory required by interleaver/deinterleaver for Reed-Solomon (RS) coded data: The memory requirements for interleavers/deinterleavers are directly related to parameters like interleaver depth and codeword size, which are fundamental to error correction (e.g., for RS codes). Determining these requirements is inherent to the design and operation of any interleaver/deinterleaver, whether dedicated or shared.
3. Allocating a first number of bytes of shared memory to an interleaver/deinterleaver (not exceeding maximum): Given the motivation to share resources, allocating a portion of a common memory pool to an interleaver or deinterleaver is a direct application of dynamic resource allocation techniques. The constraint that the allocation does not exceed a specified maximum is a standard practice in resource management.
4. Allocating a second number of bytes of shared memory to a deinterleaver/interleaver: This element further exemplifies the shared memory concept, where different functional units (transmitter-side interleaver and receiver-side deinterleaver, or multiple interleavers/deinterleavers) draw from the same memory pool.
5. Simultaneous interleaving/deinterleaving using allocated shared memory: In a full-duplex transceiver, transmit (interleaving) and receive (deinterleaving) operations occur concurrently. If a shared memory is allocated for both, their simultaneous use of their respective portions is a natural consequence of the transceiver's operation.
6. Determining allocation based on communication parameters (impulse noise protection, latency, BER) (Claims 2-4, 6-8): U.S. Pat. No. 6,775,320 already establishes that different applications have different QoS requirements (latency, BER, data rate). Since interleaver memory directly impacts these parameters (e.g., larger interleaver depth improves burst error correction but increases latency), it would be an obvious design choice for a PHOSITA to base the allocation of shared memory on these known application-specific requirements.

Conclusion:
The combination of the multi-latency path architecture described in U.S. Pat. No. 6,775,320 (or U.S. Pat. No. 6,778,589) with the pervasive general knowledge of resource sharing, dynamic allocation, and communication negotiation in computing and telecommunication systems would render the claims of US7836381 obvious to a PHOSITA. The motivation to combine these elements stems from the recognized problem of inefficient resource utilization in dedicated multi-path systems, leading to a predictable solution of implementing shared, dynamically allocated resources with appropriate inter-transceiver communication for configuration.