Prior art — US Patent 7777557

Here's an analysis of the most relevant prior art for US Patent 7777557, based on the provided patent text. The analysis focuses on how each cited reference potentially anticipates claims under 35 U.S.C. § 102, considering the inventive step of US7777557 in controlling N-well potentials using an analog comparison circuit for two parallel boosting cell rows.

The "BACKGROUND OF THE INVENTION" section of US7777557 explicitly references US Pat. Nos. 6,100,557, 6,121,821, and 7,102,422 as conventional booster circuits employing triple-well structure switching elements. The problem US7777557 aims to solve in these conventional circuits is the charging/discharging of the N-well's parasitic capacitance (due to the N-well being connected to the source) and the resulting increase in current consumption and layout area. Therefore, these three patents, along with others addressing body effects or parallel pumping, are considered highly relevant.

Most Relevant Prior Art for US7777557

1. US6100557A

Full Citation: US6100557A, "Triple well charge pump," Macronix International Co., Ltd., published August 8, 2000.
Publication/Filing Date: Publication date: 2000-08-08; Priority date: 1996-10-10.
Brief Description: This patent describes a charge pump utilizing a triple-well structure. As mentioned in the background of US7777557, this type of conventional circuit typically connects the N-well of the charge transfer transistor to its source, leading to parasitic capacitance issues and increased layout area due to the need for separate N-wells.
Potential Anticipation (35 U.S.C. § 102): US6100557A likely anticipates the general components of a booster circuit, including boosting cells with a triple-well structure and switching elements for charge transfer, as broadly described in the preambles of claims 1, 13, and 14 of US7777557. However, it does not appear to anticipate the distinguishing feature of US7777557, which is the use of an analog comparison circuit to compare potentials between boosting cells on the same stage of two parallel rows and apply a derived well bias potential to the first well region (N-well) of the switching elements, thereby reducing parasitic capacitance and enabling N-well sharing.

2. US6121821A

Full Citation: US6121821A, "Booster circuit for semiconductor device," Nec Corporation, published September 19, 2000.
Publication/Filing Date: Publication date: 2000-09-19; Priority date: 1998-03-31.
Brief Description: This patent discloses a booster circuit for semiconductor devices, also noted in US7777557 as a conventional example utilizing a triple-well structure. Similar to US6100557A, it is implied that this circuit would exhibit the N-well biasing problems that US7777557 seeks to overcome.
Potential Anticipation (35 U.S.C. § 102): US6121821A would likely anticipate the fundamental elements of a booster circuit with triple-well switching elements and the concept of charge transfer. It would not, however, anticipate the specific well-biasing scheme of US7777557, which involves an analog comparison circuit comparing potentials across two boosting cell rows to generate a controlled N-well bias, as specified in claims 1, 13, and 14.

3. US7102422B1

Full Citation: US7102422B1, "Semiconductor booster circuit having cascaded MOS transistors," Nippon Steel Corporation, published September 5, 2006.
Publication/Filing Date: Publication date: 2006-09-05; Priority date: 1994-04-20.
Brief Description: This patent describes a semiconductor booster circuit with cascaded MOS transistors, also identified in US7777557's background as conventional prior art employing triple-well switching elements. It is expected to share the N-well related limitations of other conventional triple-well designs.
Potential Anticipation (35 U.S.C. § 102): US7102422B1 likely anticipates the use of cascaded switching elements in a booster circuit and the application of MOS transistors in such a configuration, including triple-well structures. It is unlikely to anticipate the novel N-well potential control via an analog comparison circuit comparing potentials from two parallel boosting cell rows, which is central to claims 1, 13, and 14 of US7777557.

4. US6878981B2

Full Citation: US6878981B2, "Triple-well charge pump stage with no threshold voltage back-bias effect," Tower Semiconductor Ltd., published April 12, 2005.
Publication/Filing Date: Publication date: 2005-04-12; Priority date: 2003-03-20.
Brief Description: This patent specifically addresses the reduction of threshold voltage back-bias effects in a triple-well charge pump stage. This is directly related to the "substrate biasing effect" and efficiency concerns that US7777557 aims to improve.
Potential Anticipation (35 U.S.C. § 102): US6878981B2 would likely anticipate solutions for mitigating body/back-bias effects in triple-well charge pumps to improve efficiency. However, it is unlikely to anticipate the specific mechanism employed by US7777557: using an analog comparison circuit that compares potentials (output/input/intermediate) between boosting cells in two distinct parallel rows to generate and apply a well bias potential to the first well region (N-well) of switching elements, enabling common N-well sharing and reduced parasitic capacitance. While addressing a similar problem, the inventive solution of US7777557 appears distinct from what is implied by the title and general problem of US6878981B2.

5. US6888400B2

Full Citation: US6888400B2, "Charge pump circuit without body effects," Ememory Technology Inc., published May 3, 2005.
Publication/Filing Date: Publication date: 2005-05-03; Priority date: 2002-08-09.
Brief Description: This patent describes a charge pump circuit designed to operate "without body effects." This directly relates to a primary problem US7777557 also seeks to mitigate (substrate biasing effect).
Potential Anticipation (35 U.S.C. § 102): US6888400B2 would likely anticipate methods for reducing body effects in charge pump circuits, potentially using various techniques. However, it is unlikely to anticipate the specific well-biasing method of US7777557, which relies on an analog comparison circuit evaluating potentials between two parallel boosting cell rows to control the N-well potentials and allow for shared N-well regions, as defined in claims 1, 13, and 14.

6. US6952129B2

Full Citation: US6952129B2, "Four-phase dual pumping circuit," Ememory Technology Inc., published October 4, 2005.
Publication/Filing Date: Publication date: 2005-10-04; Priority date: 2004-01-12.
Brief Description: This patent describes a "dual pumping circuit" operating with "four-phase" clock signals. The "dual pumping" aspect suggests a parallel or two-row structure, which is a key component of US7777557's claims.
Potential Anticipation (35 U.S.C. § 102): US6952129B2 could anticipate the structural concept of having multiple (e.g., two) parallel boosting cell rows, potentially fulfilling parts of the preambles of claims 1, 13, and 14. It may also anticipate the use of multi-phase clocking. However, it is unlikely to anticipate the specific function of an analog comparison circuit comparing potentials between these dual pumping rows to generate a well bias potential for the first well regions (N-wells), which is the core inventive feature of US7777557, enabling reduced parasitic capacitance and shared N-wells.

7. US7123077B2

Full Citation: US7123077B2, "Four-phase charge pump circuit with reduced body effect," Ememory Technology Inc., published October 17, 2006.
Publication/Filing Date: Publication date: 2006-10-17; Priority date: 2004-08-03.
Brief Description: This patent combines aspects of multi-phase operation (four-phase) with the goal of achieving a "reduced body effect" in a charge pump circuit.
Potential Anticipation (35 U.S.C. § 102): US7123077B2 likely anticipates four-phase charge pump circuits and general methods for reducing body effects in such circuits. While addressing similar problems of efficiency and body effect, its inventive solution, as implied by the title, would likely not encompass the specific N-well biasing using an analog comparison circuit that compares potentials between two parallel boosting cell rows, which is unique to US7777557's claims 1, 13, and 14.

The remaining cited patents, while relevant to charge pump technology, do not appear from their titles or the context in US7777557 to directly address the specific problem and solution of N-well potential control via cross-row analog comparison:

US6501325B1: "Low voltage supply higher efficiency cross-coupled high voltage charge pumps," Cypress Semiconductor Corp., published December 31, 2002. (Focus on efficiency, cross-coupling may be relevant to parallel structure but likely lacks the specific N-well control.)
US6734717B2: "Charge pump circuit," Hynix Semiconductor Inc., published May 11, 2004. (Generic title, no specific indication of the N-well control mechanism.)
US20070096796A1: "High voltage charge pump with wide range of supply voltage," Firmansyah Teezar R, published May 3, 2007. (Focus on wide voltage range, not specific N-well control.)
US7317347B2: "Charge pump circuit with reuse of accumulated electrical charge," Stmicroelectronics S.R.L., published January 8, 2008. (Focus on charge reuse for efficiency, different mechanism.)
US7532062B2: "Semiconductor charge pump using MOS (metal oxide semiconductor) transistor for current rectifier device," Kabusiki Kaisha Toshiba, published May 12, 2009 (priority date November 8, 2005). (Focus on MOS transistors as rectifiers; while US7777557 uses MOS as switching elements, the core invention lies elsewhere.)