Obviousness — US Patent 7777557

To analyze the obviousness of US patent 7777557 under 35 U.S.C. § 103, we must identify combinations of prior art references that would render the claims obvious and articulate the motivation a person having ordinary skill in the art (POSITA) would have had to combine them at the time of the invention (priority date: January 17, 2007).

Prior Art References Considered

The "Description of the Related Art" section of US7777557 explicitly cites the following as conventional booster circuits employing triple-well structures:

US Pat. No. 6,100,557 (US6100557A): "Triple well charge pump"
US Pat. No. 6,121,821 (US6121821A): "Booster circuit for semiconductor device"
US Pat. No. 7,102,422 (US7102422B1): "Semiconductor booster circuit having cascaded MOS transistors"

Inventive Features of US7777557

The present invention, as summarized and defined by its independent claims (Claims 1, 13, and 14), focuses on a booster circuit comprising:

Boosting cells each having a first-conductivity type first well region (e.g., N-well) on a substrate, a second-conductivity type second well region (e.g., P-well) in the first well region, and at least one switching element.
A first boosting cell row and a second boosting cell row.
At least one analog comparison circuit for outputting a "well bias potential" by comparing:
- Output potentials of boosting cells on the same stage of the first and second rows (Claim 1).
- Intermediate potentials of backflow preventing circuits of the first and second rows (Claim 13).
This well bias potential is applied to the first well region (N-well) of the switching element(s) in the boosting cells, backflow preventing circuits, or other relevant stages.
The overall objective is to suppress current consumption and layout area while suppressing the substrate biasing effect of the switching elements, specifically by fixing the N-well potential to the input or output potential of the boosting cell stage to reduce charge/discharge between the N-well and the substrate, thereby improving boost efficiency.

Obviousness Analysis under 35 U.S.C. § 103

A person having ordinary skill in the art (POSITA) at the time of the invention would have been motivated to combine the teachings of the cited prior art with general knowledge in the field to arrive at the claimed invention.

Combination: US6100557A (or US6121821A) in view of general knowledge of multi-stage/parallel charge pump architectures and basic analog comparison circuits.

Motivation for Combination and Obviousness of Claim 1:

Triple-Well Switching Elements and N-Well Biasing: The use of triple-well structures in switching elements to mitigate the body effect and enhance charge pump efficiency was well-known in the prior art. For instance, US Pat. No. 6,100,557 explicitly teaches a "triple well charge pump" that connects the P-well to the source and the N-well to a "boosted voltage" to avoid the body effect and provide high voltage breakdown. Similarly, US Pat. No. 6,121,821 describes a booster circuit where "the potential of the N-well 221 is increased to the output voltage Vout... This prevents generation of a forward bias in the PN junction formed by the N-well 221 and the P-well 222," thereby improving efficiency. These references establish a clear motivation for a POSITA to control the potential of the N-well (the "first well region" in US7777557) based on circuit potentials to optimize performance.
Multi-Stage and Parallel Charge Pump Architectures: Charge pump circuits commonly employ multiple stages to achieve higher output voltages, faster boosting, and reduced ripple. US Pat. No. 7,102,422 describes a "semiconductor booster circuit having cascaded MOS transistors". The concept of parallel or interleaved boosting cell rows, often driven by different clock phases, is a conventional design choice in charge pumps to improve current delivery and reduce ripple. US7777557 itself depicts a "two-parallel booster circuit" (FIG. 1, 101) as its exemplary configuration and refers to conventional multi-stage designs (FIG. 25), indicating that such architectures were familiar to a POSITA.
Addressing Known Problems in Conventional N-Well Biasing: US7777557 identifies a key problem with conventional triple-well booster circuits where "the source and the N well 908 of the charge transfer transistor 906 are connected to each other, so that a parasitic capacitance formed by the N well 908 is charged and discharged by voltage transition widths of the clock signals CLK 1 and CLK 2". This parasitic capacitance "disadvantageously result[s] in a decrease in boost efficiency". A POSITA, recognizing this problem in a parallel charge pump architecture, and being aware of the prior art's teaching on N-well biasing for efficiency, would be motivated to find a dynamic control scheme for the N-wells.
Dynamic N-Well Control via Analog Comparison: In a parallel boosting cell row configuration where stages operate with different clock phases, the potentials at corresponding stages will fluctuate independently. To provide an optimal N-well bias that minimizes parasitic charge/discharge while ensuring proper operation (e.g., preventing forward bias), a POSITA would find it obvious to employ a standard analog comparison circuit. Such a circuit, a common building block in analog design, could be used to compare the output potentials of the two parallel stages at a given "i-th" stage.
- If the goal is to prevent any forward bias across the N-well (as suggested by US6121821A), a POSITA would choose the higher of the two compared potentials to apply to the N-well, ensuring it remains sufficiently biased above the P-well potential.
- If the goal is to minimize the N-well potential swing to reduce parasitic capacitance and current consumption (as stated in US7777557's summary of the invention), a POSITA would choose the lower of the two potentials (provided it still maintains a safe bias relative to the P-well). The choice between "higher" or "lower" is a predictable design optimization depending on specific performance trade-offs, making both options obvious applications of known comparison techniques to address a known problem with known N-well biasing benefits.

Therefore, the combination of a known triple-well charge pump (US6100557A or US6121821A) with conventional multi-stage/parallel architectures and basic analog comparison circuitry to dynamically control the N-well potential by comparing potentials from parallel stages, specifically to improve efficiency and reduce parasitic capacitance, would have been obvious to a POSITA. This renders Claim 1 obvious.

Obviousness of Claim 13:
Claim 13 introduces "backflow preventing circuits" into the boosting cell rows and states that the analog comparison circuit compares "intermediate potentials" of these backflow preventing circuits, applying the well bias potential to their switching elements. Backflow preventing circuits are a standard component in charge pumps, explicitly shown as "905" in the conventional circuit of US7777557 (FIG. 25). Given the general motivation to improve the efficiency and reduce parasitic effects in all switching elements within a booster circuit, extending the N-well biasing scheme, including the dynamic control via an analog comparison circuit, to the switching elements within backflow preventing circuits would be an obvious design choice for a POSITA. Comparing "intermediate potentials" of these circuits is analogous to comparing output potentials of boosting cells, as both serve the purpose of deriving a suitable bias for the N-wells in that part of the circuit. Thus, Claim 13 would also be obvious.

Obviousness of Claim 14:
Claim 14 broadly claims a booster circuit where the potential of the first well region (N-well) of switching elements in the boosting cells of both the first and second boosting cell rows is "controlled according to an output potential of the boosting cells of the first boosting cell row and an output potential of the boosting cells of the second boosting cell row." This claim is a broader articulation of the N-well control principle. As established, US Pat. No. 6,121,821 already teaches controlling the N-well potential to the output voltage (Vout). Extending this principle to control the N-wells in a parallel architecture "according to" the output potentials of both parallel rows is a straightforward application of known N-well biasing techniques to address efficiency problems in such structures. The specific analog comparison circuit described in Claim 1 is one obvious method for achieving this broader "control according to" the output potentials, but other known control mechanisms could also be employed to achieve this, making the claim broadly obvious. Thus, Claim 14 would also be obvious.