Obviousness

Obviousness Analysis of US Patent 7,745,847 Under 35 U.S.C. § 103

This analysis addresses the obviousness of US patent 7,745,847 (hereinafter '847 patent) under 35 U.S.C. § 103, based solely on the prior art references listed in the "Citations" section of the '847 patent and the description of the prior art contained within the '847 patent itself.

The '847 Patent's Independent Claim

Claim 1 of US7745847B2, the independent claim for the MOS transistor structure, recites:
"1. A MOS transistor structure, comprising:
a gate formed on a semiconductor substrate;
two raised epitaxial layers positioned respectively in the semiconductor substrate next to the relative sides of the gate and above the surface of the semiconductor substrate;
a spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layers, and a contact surface of the raised epitaxial layers and a bottom of the spacer is above the surface of the semiconductor substrate; and
two doped region formed respectively in the semiconductor substrate next to the relative sides of the gate."

The '847 patent's background describes the problem it aims to solve: conventional methods for obtaining strained channels (e.g., epitaxially growing a SiGe layer adjacent to spacers after forming the spacers) have difficulty achieving the required extent of compressive or tensile stress for improved carrier mobility. The invention's solution, as highlighted in its detailed description, is to form the epitaxial layer before the spacer, leading to a specific structural arrangement where the spacer extends laterally upon a portion of the raised epitaxial layer.

Combination of Prior Art References

A person having ordinary skill in the art (PHOSITA) would have found the structure of Claim 1 of the '847 patent obvious in view of the combination of:

• US 6,429,084 B1 (IBM - '084 patent), titled "MOS transistors with raised sources and drains"
• US 6,110,787 A (Chartered Semiconductor Manufacturing Ltd. - '787 patent), titled "Method for fabricating a MOS device"
• General knowledge in the art regarding the benefits of strained epitaxial layers in MOS transistors, as acknowledged in the background of the '847 patent.

Reasoning for Obviousness

1. Gate formed on a semiconductor substrate: This fundamental element of a MOS transistor is universally known and taught by numerous prior art references, including the '787 patent, which describes a "Method for fabricating a MOS device".

2. Two raised epitaxial layers positioned respectively in the semiconductor substrate next to the relative sides of the gate and above the surface of the semiconductor substrate: The '084 patent explicitly teaches "MOS transistors with raised sources and drains". A PHOSITA would readily understand that these "raised sources and drains" are positioned adjacent to the gate. Furthermore, given the problem in the art (improving carrier mobility through mechanical stress in the channel, as described in the '847 patent's background), a PHOSITA would know that such raised source/drain regions are commonly formed using epitaxial growth, particularly with materials like SiGe or SiC, to induce strain. The term "raised" inherently means the structures are "above the surface of the semiconductor substrate."

3. A spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layers, and a contact surface of the raised epitaxial layers and a bottom of the spacer is above the surface of the semiconductor substrate: The formation of spacers on the sidewalls of a gate is a standard and routine fabrication step in MOS technology, as would be understood from general knowledge in the field or taught by a generic MOS fabrication patent like the '787 patent. Given the teaching of "raised sources and drains" from the '084 patent, a PHOSITA, when integrating these raised structures with a standard gate and spacer configuration, would find it a natural and expected outcome, or a straightforward design choice, for the subsequently formed spacers to extend laterally onto a portion of these pre-existing raised regions. The specific geometric requirement that "a contact surface of the raised epitaxial layers and a bottom of the spacer is above the surface of the semiconductor substrate" is an inherent consequence of the epitaxial layers themselves being "raised" above the substrate surface, meaning any spacer sitting on them would also have its bottom surface above the original substrate surface.

4. Two doped region formed respectively in the semiconductor substrate next to the relative sides of the gate: Doped source/drain regions are essential components of any MOS transistor, as taught by the '787 patent. Furthermore, US 6,774,000 B2 (IBM - '000 patent), also cited as prior art, specifically teaches a "Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures," directly disclosing doped regions within raised structures.

Motivation to Combine

A PHOSITA would have been motivated to combine the teachings of the '084 patent and the '787 patent, coupled with general knowledge in the art, to produce a high-performance MOS transistor. The '084 patent teaches the benefit of "raised sources and drains", which can reduce parasitic resistance and improve gate control. The '787 patent teaches the general fabrication of MOS devices, including gates and spacers. The background of the '847 patent itself highlights the well-known objective of enhancing carrier mobility by introducing mechanical stress, often achieved through epitaxial growth of materials like SiGe or SiC in the source/drain regions.

Therefore, a PHOSITA would recognize the desirability of combining these known features: employing raised source/drain structures (for improved device geometry and reduced resistance) that are formed epitaxially (for strain-induced mobility enhancement). In such a combined structure, the resulting physical arrangement where spacers, formed on the gate sidewalls, extend laterally over a portion of these pre-existing raised epitaxial source/drain regions would be an expected and obvious outcome of integrating these known elements in a functional MOS transistor. This integration would involve routine engineering choices to optimize device characteristics, not an inventive step. The claimed structure represents a straightforward arrangement of known components, and their spatial relationship would be an obvious design consideration for a PHOSITA seeking to integrate these features for improved performance.