Patent 7745847

Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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The following is an analysis of the prior art cited in US patent 7745847, focusing on potential anticipation of its claims under 35 U.S.C. § 102. The effective filing date of US7745847 is 2007-08-09. All cited references predate this filing date.

The analysis of potential anticipation is primarily based on the titles of the cited patents, as detailed abstracts or full texts of the cited prior art were not retrieved by direct search for this task.

Claims of US7745847 for Reference:

The independent claim for the structure in US7745847 is Claim 1:

  1. A MOS transistor structure, comprising:
    • a gate formed on a semiconductor substrate;
    • two raised epitaxial layers positioned respectively in the semiconductor substrate next to the relative sides of the gate and above the surface of the semiconductor substrate;
    • a spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layers, and a contact surface of the raised epitaxial layers and a bottom of the spacer is above the surface of the semiconductor substrate; and
    • two doped region formed respectively in the semiconductor substrate next to the relative sides of the gate.

Dependent claims (2-11) elaborate on features of the gate, the type of MOS transistor (PMOS/NMOS), the material of the epitaxial layer (SiGe/SiC), details of the spacer (offset, oxide liner/nitride, L-shaped), the alignment of epitaxial layers and spacer, and the presence of lightly doped drains.

Most Relevant Prior Art for US7745847

  1. US6110787A

    • Full Citation: US6110787A, "Method for fabricating a MOS device"
    • Publication/Filing Date: Publication: 2000-08-29; Priority: 1999-09-07
    • Brief Description: This patent describes a general method for fabricating a MOS device.
    • Potential Anticipation: Based solely on the title, this patent describes a method for fabricating a MOS device. Without further details on whether it includes raised epitaxial layers next to the gate with spacers extending laterally upon them and above the substrate surface, it is unlikely to fully anticipate the structural Claim 1. It might anticipate the broader concept of forming a gate on a substrate and doped regions, which are common elements of MOS transistors.

  2. US6429084B1

    • Full Citation: US6429084B1, "MOS transistors with raised sources and drains"
    • Publication/Filing Date: Publication: 2002-08-06; Priority: 2001-06-20
    • Brief Description: This patent describes MOS transistors featuring raised sources and drains.
    • Potential Anticipation: This patent is highly relevant as it explicitly mentions "raised sources and drains," which aligns with the "two raised epitaxial layers" of US7745847's Claim 1. If these raised sources and drains are formed epitaxially and positioned next to the gate, and if the spacers interact with them in a manner where the bottom of the spacer is above the substrate surface, it could potentially anticipate Claim 1 and its dependent claims related to the nature of the epitaxial layers (e.g., Claim 3, 4, 5, 6) and general structure (Claim 2). The specific lateral extension and height details would need a deeper review of the full patent.

  3. US6774000B2

    • Full Citation: US6774000B2, "Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures"
    • Publication/Filing Date: Publication: 2004-08-10; Priority: 2002-11-20
    • Brief Description: This patent details a manufacturing method for MOSFET devices that includes in-situ doped, raised source and drain structures.
    • Potential Anticipation: Similar to US6429084B1, this patent is highly relevant due to "raised source and drain structures." The "in-situ doped" aspect also directly relates to the optional in-situ doping mentioned in US7745847's description for forming source/drain regions. This could potentially anticipate Claim 1 (due to raised epitaxial layers/source-drain structures), Claim 2 (general gate structure), and particularly Claims 3, 4, 5, 6, and 11 (related to the doping and type of transistor/epitaxial material if those materials are disclosed). The method claim of US7745847, while not asked for here, would also find this highly relevant.

  4. US6815770B1

    • Full Citation: US6815770B1, "MOS transistor having reduced source/drain extension sheet resistance"
    • Publication/Filing Date: Publication: 2004-11-09; Priority: 2003-08-14
    • Brief Description: This patent describes a MOS transistor design focused on reducing source/drain extension sheet resistance.
    • Potential Anticipation: While it addresses source/drain extensions, the title does not explicitly mention "raised epitaxial layers" or the specific spacer configuration of Claim 1 of US7745847. It might anticipate the "doped region" element of Claim 1 and general MOS transistor features (e.g., gate on substrate) but is less likely to anticipate the specific structural elements of the raised epitaxial layers and spacer interaction.

  5. US20050156154A1

    • Full Citation: US20050156154A1, "Protecting Silicon Germanium Sidewall with Silicon for Strained Silicon/Silicon Germanium MOSFETs"
    • Publication/Filing Date: Publication: 2005-07-21; Priority: 2004-01-16
    • Brief Description: This publication describes a technique for protecting silicon germanium (SiGe) sidewalls with silicon in strained Si/SiGe MOSFETs.
    • Potential Anticipation: This reference is relevant to the use of SiGe for PMOS transistors to induce strain, which aligns with Claim 4 of US7745847. If the SiGe layers are "raised epitaxial layers" as described in Claim 1, it could anticipate Claim 1 and its dependent claims related to PMOS and SiGe (Claims 3 and 4). However, the title primarily focuses on sidewall protection rather than the raised nature of the source/drain itself or the specific spacer configuration.

  6. US20060211245A1

    • Full Citation: US20060211245A1, "Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect"
    • Publication/Filing Date: Publication: 2006-09-21; Priority: 2003-12-03
    • Brief Description: This publication describes a method for forming abrupt junctions in semiconductor devices using a silicide growth dopant snowplow effect.
    • Potential Anticipation: This reference focuses on junction formation and doping profiles. While relevant to the "doped region" element of Claim 1, it does not explicitly disclose "raised epitaxial layers" or the specific spacer geometry of US7745847. Therefore, it is unlikely to anticipate Claim 1 as a whole, but might be relevant to the formation of the doped regions within the structure.

  7. US7195985B2

    • Full Citation: US7195985B2, "CMOS transistor junction regions formed by a CVD etching and deposition sequence"
    • Publication/Filing Date: Publication: 2007-03-27; Priority: 2005-01-04
    • Brief Description: This patent describes the formation of CMOS transistor junction regions using a CVD etching and deposition sequence.
    • Potential Anticipation: This reference discusses CMOS transistor junction formation using CVD and etching. This is a general method. Unless the "deposition sequence" specifically involves raised epitaxial layers that interact with spacers as described in Claim 1 of US7745847, it is unlikely to anticipate Claim 1. It could be relevant to method claims of US7745847 regarding epitaxial growth or recess etching.

  8. US20070298558A1

    • Full Citation: US20070298558A1, "Method of fabricating semiconductor device and semiconductor device"
    • Publication/Filing Date: Publication: 2007-12-27; Priority: 2006-06-22
    • Brief Description: This publication describes a method for fabricating a semiconductor device and the resulting device.
    • Potential Anticipation: The general title makes it difficult to assess specific anticipation without further detail. It broadly covers semiconductor device fabrication and the device itself. It might anticipate very general aspects of MOS transistors but lacks specificity regarding "raised epitaxial layers" and their interaction with spacers as defined in Claim 1 of US7745847.

  9. US20080006818A1

    • Full Citation: US20080006818A1, "Structure and method to form multilayer embedded stressors"
    • Publication/Filing Date: Publication: 2008-01-10; Priority: 2006-06-09
    • Brief Description: This publication describes a structure and method for forming multilayer embedded stressors.
    • Potential Anticipation: This patent is relevant to the concept of stress engineering, which is the underlying goal of forming strained epitaxial layers in US7745847. If the "embedded stressors" are "raised epitaxial layers" in the context of US7745847 and the structure includes a gate and spacers interacting as defined in Claim 1, it could be highly relevant to Claim 1 and claims related to the epitaxial layer (Claims 3-6). The term "embedded" might suggest they are not necessarily "raised" above the substrate surface in the same way as in US7745847, requiring further investigation.

  10. US20080032468A1

    • Full Citation: US20080032468A1, "Mos transistor and fabrication thereof"
    • Publication/Filing Date: Publication: 2008-02-07; Priority: 2006-08-01
    • Brief Description: This publication describes a MOS transistor and its fabrication.
    • Potential Anticipation: Similar to US20070298558A1, the general title provides insufficient detail to ascertain direct anticipation of Claim 1 of US7745847 without further review of the full patent content.

  11. US20080179636A1

    • Full Citation: US20080179636A1, "N-fets with tensilely strained semiconductor channels, and method for fabricating same using buried pseudomorphic layers"
    • Publication/Filing Date: Publication: 2008-07-31; Priority: 2007-01-27
    • Brief Description: This publication describes N-type field-effect transistors (N-fets) with tensilely strained semiconductor channels, fabricated using buried pseudomorphic layers.
    • Potential Anticipation: This reference is relevant to NMOS transistors (Claim 5) and the concept of tensilely strained channels. The use of "buried pseudomorphic layers" suggests a stressor, which could be an epitaxial layer. If these layers are "raised" and the spacer interaction matches Claim 1 of US7745847, it could be highly relevant to Claim 1, and particularly Claims 5 and 6 (if SiC or another tensile strain material is used). The term "buried" might again differentiate it from "raised" as taught in US7745847.

Conclusion on Most Relevant Prior Art:

Based on the titles and their direct relevance to the key features of US7745847's independent structure claim (Claim 1), the most relevant prior art documents appear to be those that explicitly mention "raised sources and drains" or "raised source and drain structures," and those related to strain engineering using specific materials like SiGe or SiC.

  • US6429084B1 ("MOS transistors with raised sources and drains")
  • US6774000B2 ("Method of manufacture of MOSFET device with in-situ doped, raised source and drain structures")

These two patents directly address the concept of "raised" source/drain regions, which are the "raised epitaxial layers" in US7745847. Their relevance would depend on whether they also teach the specific interaction of the spacer with these raised layers, where the spacer extends laterally upon a portion of the raised epitaxial layers and its bottom is above the surface of the semiconductor substrate, as claimed in US7745847.

Additionally, patents like US20050156154A1 (SiGe for strained Si/SiGe MOSFETs), US20080006818A1 (multilayer embedded stressors), and US20080179636A1 (N-fets with tensilely strained channels using buried pseudomorphic layers) are also highly relevant due to their focus on strain engineering and specific materials (SiGe/SiC), which are details provided in the dependent claims of US7745847. Their potential to anticipate Claim 1 would depend on whether their described stressor structures are "raised epitaxial layers" that interact with spacers in the manner claimed. Without the full text of these cited patents, a definitive conclusion on complete anticipation of Claim 1 cannot be made, but they represent the strongest candidates for relevance to the inventive concept of US7745847.

Generated 5/29/2026, 8:49:27 PM