Prior art

The USPTO's Patent Public Search tool is the authoritative source for patent searches. While I cannot directly access and perform a live search on the USPTO database in the same way a human would, I can extract and present the cited prior art from the provided patent text of US7627805. The "Citations" section of the patent itself lists the prior art considered by the examiner.

Here is an analysis of the most relevant prior art cited in US Patent 7,627,805:

I. Patent Citations

1. US6785863B2

   • Full Citation: US 6,785,863 B2 (Motorola, Inc.)
   • Publication/Filing Date: Publication: August 31, 2004; Priority: September 18, 2002
   • Brief Description: This patent describes a method and apparatus for generating parity-check bits from a symbol set. It focuses on constructing parity-check matrices for block codes, particularly for efficient encoding of systematic codes, which could involve generating a parity-check matrix with a structured form suitable for encoding.
   • Potential Anticipated Claim(s) under 35 U.S.C. § 102: This patent could potentially anticipate aspects of claims 1 and 11, specifically regarding the "generating a codeword from a mother code parity check matrix" (Claim 1) and "means for generating a codeword from a mother code parity check matrix" (Claim 11), to the extent that it discloses a method or apparatus for efficiently generating parity check bits and codewords using structured parity check matrices. The specific details of the mother code and macro matrix structure (m-by-m cyclic sub-matrices, j-by-k macro matrix) in US7627805 would need to be compared against the specific matrix construction taught in US6785863B2 to determine direct anticipation.

2. US7162684B2

   • Full Citation: US 7,162,684 B2 (Texas Instruments Incorporated)
   • Publication/Filing Date: Publication: January 9, 2007; Priority: January 27, 2003
   • Brief Description: This patent describes an efficient encoder for low-density-parity-check (LDPC) codes. It focuses on techniques to simplify the encoding process for LDPC codes, which can be computationally intensive due to the large, sparse parity-check matrices involved. The emphasis is on efficient hardware implementation for encoding.
   • Potential Anticipated Claim(s) under 35 U.S.C. § 102: Similar to US6785863B2, this patent could potentially anticipate aspects of claims 1, 11, and 17. Claims 1 and 11 broadly cover methods and apparatus for generating codewords from a mother code parity check matrix and a macro matrix. The efficient encoding described in US7162684B2, particularly with respect to structured LDPC codes, could be relevant. Claim 17, which describes a communication system with an LDPC encoder, also touches upon the broader context of encoding. However, specific details of the cyclic sub-matrix structure and the row-combining techniques for rate variation in US7627805 might differentiate it.

3. US7139959B2

   • Full Citation: US 7,139,959 B2 (Texas Instruments Incorporated)
   • Publication/Filing Date: Publication: November 21, 2006; Priority: March 24, 2003
   • Brief Description: This patent describes layered low-density parity check decoding for digital communications. While US7627805 primarily focuses on encoding, a decoder is inherently linked to the encoder's structure. This patent addresses techniques for efficient decoding of LDPC codes.
   • Potential Anticipated Claim(s) under 35 U.S.C. § 102: This patent is less likely to directly anticipate claims 1 or 11, which focus on the encoding process. However, Claim 17 describes a "communications system comprising... an LDPC iterative decoder for decoding the encoded data... in accordance with a predetermined LDPC error detection structure." To the extent that the encoding structure defined in US7627805 is chosen to facilitate efficient decoding (as mentioned in the detailed description of US7627805, which states the matrix is "designed for the decoder"), US7139959B2 might be relevant for its disclosure of LDPC decoding in a communication system. Anticipation would depend on whether the specific error detection structure of US7627805's decoder is found in US7139959B2.

II. Non-Patent Citations (for context, not direct anticipation analysis as per request)

The patent also lists three non-patent literature citations:

1. Cambridge University Press 2003, Part VI Sparse Graph Codes, pp. 556-573.
2. John R. Barry, Low-Density Parity-Check Codes, Georgia Institute of Technology, Oct. 5, 2001, pp. 1-20.
3. Richardson et al., Efficient encoding of low density parity check codes, Feb. 2001, IEEE Trans. on Info. theory, vol. 47, No. 2, p. 638-656.

These non-patent references provide background on LDPC codes and efficient encoding techniques, which are foundational to the technology claimed in US7627805.