US 7624138

US Patent 7624138: Method and Apparatus for Efficient Integer Transform

Title: Method and apparatus for efficient integer transform

Assignee: Intel Corp

Inventors: Eric Debes, William W. Macy, Jonathan J. Tyler

Filing Date: December 30, 2003

Issue Date: November 24, 2009

Abstract:
A method and apparatus for efficient integer transforms of content data are disclosed. The invention involves generating multiple sums of product pairs within a destination data storage device by executing a multiply-add instruction. These product pairs are formed by multiplying data from the destination storage device with coefficients from a coefficient data storage device. The process can generate a second set of summed product pairs in another destination storage device using a second multiply-add instruction. Furthermore, adjacent summed-product pairs from the first and second storage devices can be added together by executing a horizontal-add instruction, with the results being stored in a destination storage device and optionally in a memory device.

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Plain-Language Overview of Independent Claims:

This patent includes numerous claims, with several independent claims across different categories (method, apparatus, computer program product). Here's a plain-language overview of the primary independent claims:

Claim 1 (Method):
This claim describes a method for efficiently performing integer transforms on data. It involves:

1. Using a "multiply-add" instruction to multiply individual data elements from one source with corresponding coefficients from another source, creating intermediate products. These intermediate products are then grouped into pairs and added together to produce a set of sums (sums of product pairs). These sums are stored in a designated memory area (destination data storage device).
2. Using a "horizontal-add" instruction to take the adjacent sums of product pairs (generated in the previous step) and add them together. The results of these additions are stored back into the destination memory area. The process can be applied to implement an integer transform for content data.

Claim 10 (Apparatus):
This claim describes a computing device (processor) designed for efficient integer transforms. This processor includes:

1. An execution unit capable of running instructions.
2. A decoder that interprets instructions, including a specific "multiply-add" instruction and a "horizontal-add" instruction.
3. The multiply-add instruction, when executed, causes the processor to multiply data elements from a source with coefficients and then sum pairs of these products, storing the results.
4. The horizontal-add instruction, when executed, causes the processor to add together adjacent results (e.g., adjacent 16-bit elements) produced by the multiply-add operations, and store these new results.

Claim 14 (Computer Program Product):
This claim covers a computer-readable storage medium (like a disk or flash drive) that contains instructions. When a computer runs these instructions, it performs the method described in Claim 1, meaning it executes the steps of:

1. Generating sums of product pairs using a multiply-add instruction.
2. Adding adjacent summed-product pairs using a horizontal-add instruction to achieve an integer transform.

Claim 15 (Method - focusing on a 4x4 transform):
This method claim focuses on performing a 4x4 integer transform specifically for content data. It involves:

1. Executing a first multiply-add instruction to generate initial sums of products within a destination device by multiplying data from that device with coefficients.
2. Executing a second multiply-add instruction to generate more sums of products in a second destination device.
3. Executing a first horizontal-add instruction to add adjacent pairs of sums from the first destination device and store the results.
4. Executing a second horizontal-add instruction to add adjacent pairs of sums from the second destination device and store the results.
5. Storing these final results in a memory device.

Claim 20 (Apparatus - focusing on a 4x4 transform):
This apparatus claim describes a processor configured to perform a 4x4 integer transform on content data. It has:

1. A memory for storing data and instructions.
2. A processor coupled to the memory, containing an execution unit and a decoder.
3. The processor is configured to perform the steps outlined in Claim 15, specifically executing the two multiply-add and two horizontal-add instructions to compute the 4x4 transform.

There is no authoritative information from the CAFC 2026 dockets indicating any ongoing legal challenges or appeals related to US patent 7624138. The patent's legal status is "Expired - Lifetime", with an expiration date of May 5, 2024.