Prior art

To identify the most relevant prior art for US Patent 7579227, an examination of the "Prior art citations" section from the Google Patents entry for US7579227 was conducted. The core innovation of US7579227, as articulated in its independent claims (Claims 1 and 9), revolves around a semiconductor device featuring a high dielectric constant gate insulating film that is continuously formed from under the gate electrode to under the insulating sidewall, with the crucial aspect being that the portion under the sidewall has a smaller thickness than the portion under the gate electrode. The related method claims describe etching to achieve this reduced thickness.

Several prior art patents from the same original assignee, Panasonic Corp (or its earlier name Matsushita Electric Industrial Co., Ltd.), were identified that directly address this specific structural and methodological feature. The most relevant patents are those that explicitly disclose a non-uniform high-dielectric-constant gate insulating film where the thickness under the sidewall is reduced compared to the thickness under the gate electrode.

The following patents are considered most relevant:

1. US6975005B2

   • Full Citation: US6975005B2, "Method for manufacturing semiconductor device"
   • Publication Date: 2005-12-13
   • Filing Date: 2004-03-26
   • Brief Description: This patent describes a method for manufacturing a semiconductor device where the gate insulating film has a non-uniform thickness. Specifically, the thickness of the gate insulating film portion between the gate electrode and the semiconductor substrate is larger than the thickness of the portion between the sidewall and the semiconductor substrate.
   • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates Claim 1 of US7579227 by explicitly disclosing a semiconductor device where the gate insulating film has a smaller thickness under the sidewall than under the gate electrode. It also implicitly anticipates aspects of Claim 9 as it describes a method resulting in this specific structure. The filing date of US6975005B2 (2004-03-26) predates the priority date of US7579227 (2005-08-05), making it effective prior art.

2. US6930006B2

   • Full Citation: US6930006B2, "Method for fabricating semiconductor device"
   • Publication Date: 2005-08-16
   • Filing Date: 2004-01-28
   • Brief Description: This patent discloses a method for fabricating a semiconductor device that involves forming a gate insulating film with a non-uniform thickness over a semiconductor substrate, a gate electrode on the film, and sidewalls on the side faces of the gate electrode. The thickness of the gate insulating film portions located under the sidewalls is smaller than that of the portion located under the gate electrode.
   • Potential Anticipation (35 U.S.C. § 102): This patent potentially anticipates Claim 1 of US7579227 due to its clear disclosure of the gate insulating film being thinner under the sidewalls than under the gate electrode. As a method patent, its description of forming such a structure also potentially anticipates Claim 9. Its filing date (2004-01-28) predates the priority date of US7579227.

3. US6902996B2

   • Full Citation: US6902996B2, "Method for fabricating semiconductor device"
   • Publication Date: 2005-06-07
   • Filing Date: 2004-01-28
   • Brief Description: This patent describes a method of fabricating a semiconductor device including forming a gate insulating film over a semiconductor substrate and a gate electrode over the film, then forming sidewalls. The gate insulating film is formed to have a non-uniform thickness, with the portion under the gate electrode being thicker than the portion under the sidewalls.
   • Potential Anticipation (35 U.S.C. § 102): Similar to the above, this patent potentially anticipates Claim 1 of US7579227 by describing the key structural feature of a gate insulating film with reduced thickness under the sidewalls. Its method-oriented claims and description also strongly suggest anticipation of Claim 9. Its filing date (2004-01-28) predates the priority date of US7579227.

4. US20040222475A1

   • Full Citation: US20040222475A1, "Semiconductor device and method of fabricating the same"
   • Publication Date: 2004-11-11
   • Filing Date: 2003-05-05
   • Brief Description: This patent application describes a semiconductor device comprising a gate electrode on a semiconductor substrate with a gate insulating film, and a side insulating film (sidewall) on a side surface of the gate electrode. The gate insulating film has a non-uniform thickness, where the portion directly under the gate electrode is thicker than the portion located between the side insulating film and the semiconductor substrate.
   • Potential Anticipation (35 U.S.C. § 102): This publication potentially anticipates Claim 1 of US7579227 due to its clear disclosure of a gate insulating film having a smaller thickness under the sidewall than under the gate electrode. Given its title and abstract, it also describes a method to achieve this structure, thereby potentially anticipating Claim 9. Its publication date (2004-11-11) and filing date (2003-05-05) both predate the priority date of US7579227.

These patents are highly relevant as prior art because their abstracts explicitly describe the core inventive concept of US7579227: a gate insulating film that is thinner under the sidewall than under the gate electrode, and methods for achieving this structure. The fact that they share the same original assignee further emphasizes their close relation and potential for anticipation.