Obviousness

Under 35 U.S.C. § 103, an invention is considered obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). This analysis considers the scope and content of the prior art, the differences between the prior art and the claims, the level of ordinary skill in the art, and any secondary considerations of non-obviousness.

Prior Art References from US7579227

The patent US7579227 itself identifies and describes several pieces of prior art in its "Description of Prior Art" section and throughout the specification:

1. Ken Watanabe, HfSiON - CMOS technology for achieving high performance and high reliability, Semi. Forum Japan, 2005. This reference is explicitly cited as disclosing "known MISFETs using a high dielectric constant gate insulating film" and is illustrated in FIGS. 16A and 16B of US7579227.
   • Teachings (from US7579227's description of Watanabe):
     • FIG. 16A: A gate electrode 105 formed on an active region of a well 102 with a high dielectric constant gate insulating film 104 interposed. An insulating sidewall 107 is formed on each side of the gate electrode 105. An extension region 110 is under the sidewall 107, and source/drain regions 112 are external to the extension region.
     • FIG. 16B: Similar to FIG. 16A, but with an insulating offset sidewall 106 interposed between the gate electrode 105 and the sidewall 107, to optimize the overlapping amount between the gate electrode and an extension region.
   • Problems with Watanabe (as articulated by US7579227):
     • Side end portions of the high dielectric constant gate insulating film 104 are in direct contact with sidewalls (107 or 106/107), causing a reduction in the dielectric constant and insulation property of the high-k film at the gate electrode end, leading to deteriorated device characteristics and degraded reliability.
     • If the high dielectric constant gate insulating film 104 is kept remaining under the sidewalls, the capacitance between gate/drain regions increases, resulting in adverse effects on circuit speed.
     • Performing extension or LDD implantation through a thick high dielectric constant film (due to its material properties and required thickness) necessitates increased acceleration energy, leading to deeper junctions and suboptimal device characteristics.
2. T. Hori, IEDM Tech. Dig., 1989, p. 777. This reference is cited by US7579227 for the concept that a "high overlapping effect between a gate and a drain can be achieved" to improve device characteristics and hot carrier reliability.
3. H. Sayama et al., IEDM Tech. Dig., 2000, p. 239. This reference is cited by US7579227 in the context of "a double sidewall type MISFET in which an overlapping amount between a gate electrode and an extension region can be optimized in a simple manner".

Obviousness Analysis

The core invention of US7579227, as described in its Summary and Embodiments, aims to address the aforementioned problems by continuously forming the high dielectric constant gate insulating film from under the gate electrode to under the insulating sidewall, but with the critical modification that the part under the insulating sidewall has a smaller thickness than the part under the gate electrode.

A PHOSITA would be motivated to combine the teachings of the prior art and known semiconductor processing techniques to arrive at the claimed invention for the following reasons:

Combination 1: Watanabe (FIGS. 16A/B) + Motivation from known problems + General Semiconductor Engineering Principles

1. Primary Reference: Ken Watanabe, HfSiON - CMOS technology for achieving high performance and high reliability, Semi. Forum Japan, 2005 (as depicted in US7579227's FIGS. 16A and 16B).
   • Teachings: Watanabe discloses MISFETs with high-k gate insulating films (104) under a gate electrode (105) and extending under insulating sidewalls (107 or offset sidewall 106 and main sidewall 107). Extension regions (110) are located under these sidewalls.
   • Motivation to Modify: US7579227 explicitly identifies the problems inherent in the Watanabe structures:
     • Degradation of high-k film: The direct contact between the high-k film and sidewalls leads to degradation of dielectric constant and insulation properties. A PHOSITA would be motivated to prevent this by maintaining the continuity of the high-k film under the sidewall, thereby preventing direct contact of its side end portion with the bulk sidewall material.
     • Increased gate-drain capacitance: Merely extending a uniformly thick high-k film under the sidewall would increase parasitic capacitance and reduce circuit speed. A PHOSITA would recognize the well-known principle that reducing the thickness of a dielectric layer can decrease capacitance.
     • Difficulty with shallow junctions: The patent notes that implantation through a thick high-k film makes forming shallow junctions difficult due to increased acceleration energy requirements. A PHOSITA would understand that a thinner intervening layer would allow for lower implantation energies and consequently shallower junctions.
   • Obvious Solution: Given these clear problems, a PHOSITA would be motivated to combine the desire for high-k film continuity (to prevent degradation) with the necessity of reducing capacitance and facilitating shallow junctions. Selectively etching or thinning the portion of the high-k gate insulating film located under the sidewalls, while maintaining its continuity with the portion under the gate electrode, is a logical and straightforward engineering solution to address these recognized issues simultaneously. This directly addresses the main features of claim 1.

Obviousness of Additional Features:

• Buffer Insulating Film: The patent's fourth embodiment describes including a buffer insulating film (e.g., silicon oxide or silicon oxynitride) between the substrate and the high-k gate insulating film to improve the interface quality. The use of such buffer layers with high-k gate dielectrics was a well-established technique in semiconductor manufacturing prior to the priority date of US7579227, aimed at mitigating interface states and improving device performance and reliability. A PHOSITA would have been motivated to incorporate such a known buffer layer to enhance the device disclosed by Watanabe.
• Notch at a Side End Portion: The patent describes in its fifth embodiment that a "notch" can be formed if wet etching is used to remove part of the high dielectric constant gate insulating film. Wet etching processes, especially when performed selectively on certain materials, are known to create non-uniformities or notches at material edges. Thus, if a PHOSITA were to employ wet etching to achieve the desired thinning or removal of the high-k film, the formation of a notch would be an expected, if not inherent, outcome of a common fabrication process rather than an independent inventive feature.
• Fully Silicided (FUSI) Gate Electrode: The eighth embodiment of the patent details the fabrication of a fully silicided gate electrode. FUSI gate technology was known in the art prior to 2005/2006 as a method to reduce gate resistance and tune work functions, particularly in advanced CMOS devices employing high-k dielectrics. A PHOSITA, seeking to further optimize the performance of the MISFET structure (e.g., for speed or threshold voltage control), would have been motivated to combine the high-k/sidewall structure with a FUSI gate electrode, as these are complementary technologies for semiconductor device enhancement.

Conclusion on Obviousness

The combination of the known MISFET structures using high-k gate insulating films (as taught by Watanabe), coupled with the clear problems identified by US7579227 itself (degradation of high-k film, increased gate-drain capacitance, difficulty with shallow junctions), and the application of well-known semiconductor engineering principles (maintaining film integrity, thinning dielectrics to reduce capacitance and aid implantation, using buffer layers, employing FUSI gates), would have made the claimed invention obvious to a person having ordinary skill in the art at the time of invention. The patent effectively articulates the problems and then presents solutions that would be considered conventional responses within the skilled artisan's technical domain.