Invalidity dossier
US 7491624
Method of manufacturing low CTE substrates for use with low-k flip-chip package devices
Current assignee: RENT-A-TOLL Ltd
Added 9/23/2026, 9:35:45 PM
Active provider: DeepSeek · deepseek-flash
Patent summary
Title, assignee, inventors, filing/issue dates, abstract, and a plain-language overview of the claims.
Patent Overview — US7491624B2
Title: Method of manufacturing low CTE substrates for use with low-k flip-chip package devices
Patent number: US7491624B2 (application US11/610,752; pre-grant publication US20070087479A1)
Original assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC). The source also lists "RENT-A-TOLL Ltd" among current assignees, noting listed assignees may be inaccurate and no legal analysis was performed.
Inventors: Szu-Wei Lu, Hsin-Hui Lee, Chien-Hsiun Lee, Mirng-Ji Lii
Key dates (as listed; the source labels priority date and legal status as assumptions, not legal conclusions):
- Prior art date: 2005-07-07
- Priority date: 2005-07-07
- Filing date: 2006-12-14
- Publication of US20070087479A1: 2007-04-19
- Granted/publication of US7491624B2: 2009-02-17
- Adjusted expiration: 2026-02-28; status "Expired - Lifetime"
Purpose and plain-language scope (from the supplied text): The disclosure relates generally to semiconductor manufacturing, and more particularly to low CTE (coefficient of thermal expansion) substrates for use with low-k flip-chip semiconductor package devices.
The excerpt explains flip-chip packaging: face-down ("flipped") components connect directly to substrates such as ceramic substrates, circuit boards, or carriers via conductive solder bumps formed in a ball grid array on the chip's bondpads. It describes flip-chip as replacing older wire-bonding technology, notes bump fabrication (typically Pb/Sn solders) on aluminum bondpads, and lists bump functions: an electrically conductive path from the IC chip/die to the substrate, a thermally conductive path carrying heat from chip to substrate, part of the mechanical mounting, a spacer preventing contact between chip and substrate connectors, and a short lead relieving mechanical strain between chip and substrate. The excerpt states the flip-chip package device "can g..." and is cut off there.
What the excerpt does not establish: No claims are reproduced, so the actual claimed method and its scope are not shown. No specific low-CTE materials, CTE values, process steps, embodiments, or prior-art references are included. Inventive purpose beyond the general field statement is not established, nor is any legal conclusion on validity or coverage.
Source: https://patents.google.com/patent/[US7491624](/patent/US7491624)/en
Generated 10/1/2026, 9:34:11 PM
Cases on file (0)
Specific litigation cases in our database that name US patent 7491624. The free-form analysis below may also discuss cases beyond this list.
No cases on file mention this patent. Upload a CSV or add a case manually in Admin → Manage litigation cases.
Litigation summary
Past and pending lawsuits — plaintiffs, defendants, jurisdictions, outcomes, and notable rulings.
Proceedings on file (0)
All PTAB activity →AIA trial proceedings (IPR / PGR / CBM) filed at the USPTO Patent Trial and Appeal Board against this patent. Sourced from the USPTO Open Data Portal and refreshed every six hours; each proceeding number deep-links to the PTAB E2E docket.
No PTAB proceedings on file. This patent has not been challenged via IPR, PGR, or CBM. The absence is itself a signal — well-asserted patents eventually attract IPRs. The LLM analysis below may surface filings the ODP feed hasn’t indexed yet.
PTAB challenges
AIA trial proceedings at the USPTO Patent Trial and Appeal Board — IPR, PGR, and CBM. Petitioners, judge panels, claim-level invalidation outcomes from Final Written Decisions, and Federal Circuit appeals. The single most important defensive datapoint after litigation history.
Assignment history
Inventors, original assignee, and the chain of ownership recorded with the USPTO — including the correspondent attorney who recorded each assignment, since shell-LLC chains often share one repeat-player attorney even when the entity names look unrelated. Surfaces NPE / patent-troll patterns: shell-entity transfers, known asserters in the chain, repeat correspondent fingerprints, pre-litigation assignments, and bankruptcy fire-sales.
Prior art
Earlier patents, publications, and products that may anticipate or render the claims unpatentable.
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
Extensions
Patent term adjustments, term extensions, continuations, divisionals, family members, and expiration dates.
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.