Prior art

Most Relevant Prior Art for US Patent 7349448

As of April 26, 2026, the following prior art references are identified as most relevant to US Patent 7349448, "Distributed multiplexing circuit with built-in repeater," based on the citations listed within the patent itself. The analysis focuses on potential anticipation under 35 U.S.C. § 102.

The key innovative aspects of US7349448 include a distributed multiplexing architecture with multiple cascaded stages, the use of tristate drivers for data selection and propagation, and specifically, the "built-in repeater" functionality where certain tristate drivers increase the signal strength of the propagated data.

Here are the details for the most relevant prior art citations:

1. EP0492862A2

• Full Citation: EP0492862A2, "Daisy chain multiplexer," Hughes Aircraft Company.
• Publication/Filing Date: Priority Date: 1990-12-20; Publication Date: 1992-07-01.
• Brief Description: This patent describes a daisy chain multiplexer designed to multiplex a plurality of input signals onto an output line. It comprises multiple input modules arranged in a daisy chain. Each module has an input for a local signal, a second input for receiving a daisy chain output signal from a preceding module, a control input, and an output. Each module selects either its local input signal or the daisy chain signal from the preceding module based on the control input, and transmits the selected signal to its output, which can then feed the next module in the chain.
• Potential Anticipation (35 U.S.C. § 102): EP0492862A2 is highly relevant as it directly anticipates the fundamental architectural concept of a distributed, multi-stage multiplexer where each stage receives data from a local source and from a previous stage, and then selects one to pass forward.
  • Claims 1, 2, 8, 20, 21: These claims describe a circuit and method comprising multiple stages (first, second, third logic/stages) configured to receive a data word from a previous stage and a local data word, and to select one for transmission. The "daisy chain" structure and "receiving a daisy chain output signal from a preceding module" in EP0492862A2 directly maps to this core distributed, cascaded selection mechanism. For example, the preamble of Claim 1, "first stage logic... configured to receive the first data word from one of the connections and to transmit the first data word received; and second stage logic configured to receive the first data word from the first stage logic and to receive the second data word from another of the plurality of data connections, the second stage logic configured to select for transmission one of the first data word and the second data word," is largely anticipated.
  • The degree to which EP0492862A2 anticipates the use of tristate drivers for selection (as explicitly detailed in US7349448's Claims 1, 5, 9, 14, 17) and the built-in repeater functionality (Claims 4, 6, 19) would depend on the specific implementation details of the internal modules within EP0492862A2, which are not explicitly detailed in its abstract regarding signal strengthening by the pass-through logic.

2. US5936424A

• Full Citation: US5936424A, "High speed bus with tree structure for selecting bus driver," Xilinx, Inc.
• Publication/Filing Date: Priority Date: 1996-02-02; Publication Date: 1999-08-10.
• Brief Description: This patent describes a high-speed bus system that employs a tree structure to select one of several bus drivers to drive a bus. A select signal is propagated through a tree of selection circuitry. Each selection circuit in the tree generates an enable signal for a specific bus driver and also a "pass-through" signal to the next selection circuit in the tree, effectively distributing the control logic for driver selection.
• Potential Anticipation (35 U.S.C. § 102): US5936424A anticipates the concept of distributed selection logic and the propagation of control signals through a staged (tree-like) architecture to enable a specific driver for a bus.
  • Claims 1, 2, 8, 10, 11, 20, 21: These claims relate to the distributed selection of a data word across multiple stages based on select signals. The "tree structure for selecting bus driver" and the propagation of a "select signal" through "selection circuitry" that generates "enable signals" aligns closely with the distributed control aspect of US7349448. The "pass-through signal to the next selection circuit" is analogous to the staged nature of the select signal processing.
  • Claims 9, 12, 13: These claims address the use of tristate drivers and their concurrent enablement/disablement. As bus drivers are commonly implemented using tristate buffers, the enablement of a bus driver by a select signal generated by the tree structure anticipates aspects of these claims, particularly regarding the control of multiple drivers to avoid contention.
  • While US5936424A focuses on the control path for selecting a bus driver, rather than the explicit data path with repeaters for data words propagating through stages, the underlying principles of distributed control and selection are highly similar.

3. US5677638A

• Full Citation: US5677638A, "High speed tristate bus with multiplexers for selecting bus driver," Xilinx, Inc.
• Publication/Filing Date: Priority Date: 1996-02-02; Publication Date: 1997-10-14.
• Brief Description: This patent describes a high-speed tristate bus system that includes multiple bus drivers and a bus selection multiplexer. This multiplexer is coupled to each bus driver to select one of them to actively drive the tristate bus. The patent also addresses techniques for delay compensation on segmented buses to manage propagation delays, which are critical in high-speed environments.
• Potential Anticipation (35 U.S.C. § 102): US5677638A is highly relevant for its disclosure of using tristate drivers and multiplexers for bus selection in high-speed applications.
  • Claims 1, 5, 9, 10, 11, 12, 14, 17: These claims describe the use of tristate drivers for receiving and transmitting data words, and for selecting which data word drives a connection, based on select signals. US5677638A directly anticipates the general concept of using "tristate bus drivers" and "bus selection multiplexers" for enabling one of a plurality of drivers to control a bus. The concern for "high speed" and "delay compensation" hints at the signal integrity issues that US7349448 addresses with its repeater functionality.
  • The patent broadly covers the management of multiple drivers on a shared bus, a foundational element of multiplexing, and the application of tristate logic for this purpose.

The primary distinguishing feature of US7349448, particularly in Claims 4, 6, and 19, is the explicit "built-in repeater" functionality where the tristate drivers responsible for propagating data from a previous stage also increase the signal strength of that data. While the cited prior art addresses distributed selection, cascading architectures, and high-speed bus driving, it does not explicitly detail tristate drivers providing signal strength increase specifically when acting as pass-through elements in a multi-stage data multiplexer.